Anccend/risc-v-cpu
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risc-v-cpu/pipelined-cpu/programs/risc-v-intrupt-sllsb.asm
T
Alpha e44680a114 feat(board): 新增课程新版中断测试上板（多级中断 + 附加 SLL/SB/BLTU） 
- programs/risc-v-intrupt-sllsb.asm/.hex: 课程原始程序（344 字，hex 已去掉 Logisim
  的 v2.0 raw 头），保留原文件以便追溯
- tools/adapt_intrupt_sllsb.py: 把它适配到本 CPU 上板（只改 ROM 内容，地址不变）
  - 课程用 addi a7,zero,34 + ecall 显示，本 CPU 里那是空操作 -> 每条显示点原地换成
    一次调用：主程序 jal ra,DISP_DLY；ISR 用 add a7,a0,zero + jal a0,DISP_DLY_ISR
    （三个 ISR 都没保存 ra，所以 ISR 版把链接寄存器放 a0、显示值放 a7）
  - DISP_DLY / DISP_DLY_ISR 各 8 条，追加在 uret 之后，中断入口 0x0AC/0x240/0x3E8 不变
  - 返回地址存 sp+256（越过 ISR 最多 192 字节的栈区），嵌套中断也破坏不了
  - 脚本自带跳转目标自检（曾发现 ISR 侧 jal 偏移少算一条指令的问题）
- srcs/board/cpu21_board_top.v: 新增 RISC_V_INTRUPT_SLLSB_ROM 分支（ROM 选择、
  CPU 分频用 CLK_DIV_INTRUPT、中断向量 0x0AC/0x240/0x3E8）
- srcs/board/risc-v-intrupt-sllsb.vh: 生成的 ROM 初始化（1024 字，程序 360 字）
- create_project.tcl: 新增 use_intrupt_sllsb 开关（默认 1，已把 ccab 置 0）

实测：Vivado 2020.2 建工程 + 综合通过（sources_1 verilog_define =
RISC_V_INTRUPT_SLLSB_ROM，synth_design Complete! 100%）
2026-09-19 16:10:19 +08:00

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.text
addi sp, zero, 2000 #�ڴ��ջ��ʼ��
#############################################################
#�����Ʋ�?,����addi,andi,slli,srli,srai,or,ori,nor,ecall LED�������Ʒ�ʽ������ʾ����
#############################################################
.text
START:
addi s0,zero,1
slli s3, s0, 31 # s3=0x80000000
srai s3, s3, 31 # s3=0xFFFFFFFF
add s0,zero,zero # s0=0
addi s2,zero,12
addi s6,zero,8 #�����Ƽ���
zmd_loop:
addi s0, s0, 1 #������һ�������Ƶ���
andi s0, s0, 15
#######################################
addi t0,zero,8
addi t1,zero,1
left:
slli s3, s3, 4 #����������
or s3, s3, s0
add a0,zero,s3 # display s3
addi a7,zero,34 # system call for LED display
ecall # display
sub t0,t0,t1
bne t0,zero,left
#######################################
addi s0, s0, 1 #������һ�������Ƶ���
addi t6,zero,15
and s0, s0, t6
slli s0, s0, 28
addi t0,zero,8
addi t1,zero,1
zmd_right:
srli s3, s3, 4 #����������
or s3, s3, s0
add a0,zero,s3 # display s3
addi a7,zero,34 # system call for LED display
ecall # display
sub t0,t0,t1
bne t0,zero,zmd_right
srli s0, s0, 28
#######################################
sub s6,s6,t1
beq s6,zero, exit
j zmd_loop
exit:
add t0,zero,zero
xori t0,t0,-1 #test nor ori
slli t0,t0,16
ori t0,t0,-1
add a0,zero,t0 # display t0
addi a7,zero,34 # system call for LED display
ecall # display
j START # loop forever
#InteruptProgram1:
#############################################################################################
# exceptoin 1
# ʹ��?s6? s5?s4?s3?s0?a0?a7
#############################################################################################
################# �����ֳ�
InteruptProgram1:sw a7, 0(sp)
addi sp, sp, 4
sw a0, 0(sp)
addi sp, sp, 4
sw s0, 0(sp)
addi sp, sp, 4
sw s3, 0(sp)
addi sp, sp, 4
sw s4, 0(sp)
addi sp, sp, 4
sw s5, 0(sp)
addi sp, sp, 4
sw s6, 0(sp)
addi sp, sp, 4
csrrsi s6,0x41,0 #s6=uepc
sw s6, 0(sp) #uepcѹջ����
addi sp, sp, 4
################# ���ж�
sw t0,0(sp)
addi sp,sp,4
sw t1,0(sp)
addi sp,sp,4
sw t2,0(sp)
addi sp,sp,4
sw t3,0(sp)
addi sp,sp,4
sw t4,0(sp)
addi sp,sp,4
sw t5,0(sp)
addi sp,sp,4
sw t6,0(sp)
addi sp,sp,4
sw s1,0(sp)
addi sp,sp,4
sw s2,0(sp)
addi sp,sp,4
csrrsi zero,0x4,1 #ustatus.MIE=1
################# �жϷ���
addi s6,zero,1 #�ж�?1,2,3 ��ͬ�жϺ���ʾֵ��һ��
addi s4,zero,3 #ѭ��������ʼֵ
addi s5,zero,1 #�������ۼ�ֵ
IntLoop1:
add s0,zero,s6
IntLeftShift1:
slli s0, s0, 4
or s3,s0,s4
add a0,zero,s3 #display s0
addi a7,zero,34 # display hex
ecall
bne s0, zero, IntLeftShift1
sub s4,s4,s5 #ѭ�������ݼ�
bne s4, zero, IntLoop1
################# ���ж�
csrrci zero,0x4,1 #ustatus.MIE=0
############### ����ָ�� ����(SLL/SB/BLTU ֮һ) ###############
addi t0,zero,1
addi t1,zero,3
addi s1,zero,0x8
slli s1,s1,8
addi s1,s1,0x76
add a0,zero,s1
addi a7,zero,34
ecall
addi t3,zero,8
sll_branch:
sll s1,s1,t0
sll s1,s1,t1
add a0,zero,s1
addi a7,zero,34
ecall
addi t3,t3,-1
bne t3,zero,sll_branch
addi sp,sp,-4
lw s2,0(sp)
addi sp,sp,-4
lw s1,0(sp)
addi sp,sp,-4
lw t6,0(sp)
addi sp,sp,-4
lw t5,0(sp)
addi sp,sp,-4
lw t4,0(sp)
addi sp,sp,-4
lw t3,0(sp)
addi sp,sp,-4
lw t2,0(sp)
addi sp,sp,-4
lw t1,0(sp)
addi sp,sp,-4
lw t0,0(sp)
################# �ָ��ֳ�
addi sp, sp, -4
lw s6, 0(sp)
csrrw zero,0x41,s6 #uepc=s6
addi sp, sp, -4
lw s6, 0(sp)
addi sp, sp, -4
lw s5, 0(sp)
addi sp, sp, -4
lw s4, 0(sp)
addi sp, sp, -4
lw s3, 0(sp)
addi sp, sp, -4
lw s0, 0(sp)
addi sp, sp, -4
lw a0, 0(sp)
addi sp, sp, -4
lw a7, 0(sp)
################ �жϷ���
uret #ͬ�����жϣ�uepc-->pc
#InteruptProgram2:
#############################################################################################
# exceptoin 2
# ʹ��?s6? s5?s4?s3?s0?a0?a7
#############################################################################################
################# �����ֳ�
InteruptProgram2:sw a7, 0(sp)
addi sp, sp, 4
sw a0, 0(sp)
addi sp, sp, 4
sw s0, 0(sp)
addi sp, sp, 4
sw s3, 0(sp)
addi sp, sp, 4
sw s4, 0(sp)
addi sp, sp, 4
sw s5, 0(sp)
addi sp, sp, 4
sw s6, 0(sp)
addi sp, sp, 4
csrrsi s6,0x41,0 #s6=uepc
sw s6, 0(sp) #uepcѹջ����
addi sp, sp, 4
################# ���ж�
sw t0,0(sp)
addi sp,sp,4
sw t1,0(sp)
addi sp,sp,4
sw t2,0(sp)
addi sp,sp,4
sw t3,0(sp)
addi sp,sp,4
sw t4,0(sp)
addi sp,sp,4
sw t5,0(sp)
addi sp,sp,4
sw t6,0(sp)
addi sp,sp,4
sw s1,0(sp)
addi sp,sp,4
sw s2,0(sp)
addi sp,sp,4
csrrsi zero,0x4,1 #ustatus.MIE=1
################# �жϷ���
addi s6,zero,2 #�ж�?1,2,3 ��ͬ�жϺ���ʾֵ��һ��
addi s4,zero,3 #ѭ��������ʼֵ
addi s5,zero,1 #�������ۼ�ֵ
IntLoop2:
add s0,zero,s6
IntLeftShift2:
slli s0, s0, 4
or s3,s0,s4
add a0,zero,s3 #display s0
addi a7,zero,34 # display hex
ecall
bne s0, zero, IntLeftShift2
sub s4,s4,s5 #ѭ�������ݼ�
bne s4, zero, IntLoop2
################# ���ж�
csrrci zero,0x4,1 #ustatus.MIE=0
############### ����ָ�� ����(SLL/SB/BLTU ֮һ) ###############
addi t1,zero,0
addi t3,zero,32
addi s1,zero,0x00
addi s2,zero,0x01
sb_store:
sb s1,0(t1)
add a0,zero,s1
addi a7,zero,34
ecall
add s1,s1,s2
addi t1,t1,1
addi t3,t3,-1
bne t3,zero,sb_store
addi t3,zero,8
addi t1,zero,0
sb_branch:
lw s1,0(t1)
add a0,zero,s1
addi a7,zero,34
ecall
addi t1,t1,4
addi t3,t3,-1
bne t3,zero,sb_branch
addi sp,sp,-4
lw s2,0(sp)
addi sp,sp,-4
lw s1,0(sp)
addi sp,sp,-4
lw t6,0(sp)
addi sp,sp,-4
lw t5,0(sp)
addi sp,sp,-4
lw t4,0(sp)
addi sp,sp,-4
lw t3,0(sp)
addi sp,sp,-4
lw t2,0(sp)
addi sp,sp,-4
lw t1,0(sp)
addi sp,sp,-4
lw t0,0(sp)
################# �ָ��ֳ�
addi sp, sp, -4
lw s6, 0(sp)
csrrw zero,0x41,s6 #uepc=s6
addi sp, sp, -4
lw s6, 0(sp)
addi sp, sp, -4
lw s5, 0(sp)
addi sp, sp, -4
lw s4, 0(sp)
addi sp, sp, -4
lw s3, 0(sp)
addi sp, sp, -4
lw s0, 0(sp)
addi sp, sp, -4
lw a0, 0(sp)
addi sp, sp, -4
lw a7, 0(sp)
################ �жϷ���
uret #ͬ�����жϣ�uepc-->pc
#InteruptProgram3:
#############################################################################################
# exceptoin 3
# ʹ��?s6? s5?s4?s3?s0?a0?a7
#############################################################################################
################# �����ֳ�
InteruptProgram3:sw a7, 0(sp)
addi sp, sp, 4
sw a0, 0(sp)
addi sp, sp, 4
sw s0, 0(sp)
addi sp, sp, 4
sw s3, 0(sp)
addi sp, sp, 4
sw s4, 0(sp)
addi sp, sp, 4
sw s5, 0(sp)
addi sp, sp, 4
sw s6, 0(sp)
addi sp, sp, 4
csrrsi s6,0x41,0 #s6=uepc
sw s6, 0(sp) #uepcѹջ����
addi sp, sp, 4
################# ���ж�
sw t0,0(sp)
addi sp,sp,4
sw t1,0(sp)
addi sp,sp,4
sw t2,0(sp)
addi sp,sp,4
sw t3,0(sp)
addi sp,sp,4
sw t4,0(sp)
addi sp,sp,4
sw t5,0(sp)
addi sp,sp,4
sw t6,0(sp)
addi sp,sp,4
sw s1,0(sp)
addi sp,sp,4
sw s2,0(sp)
addi sp,sp,4
csrrsi zero,0x4,1 #ustatus.MIE=1
################# �жϷ���
addi s6,zero,3 #�ж�?1,2,3 ��ͬ�жϺ���ʾֵ��һ��
addi s4,zero,3 #ѭ��������ʼֵ
addi s5,zero,1 #�������ۼ�ֵ
IntLoop3:
add s0,zero,s6
IntLeftShift3:
slli s0, s0, 4
or s3,s0,s4
add a0,zero,s3 #display s0
addi a7,zero,34 # display hex
ecall
bne s0, zero, IntLeftShift3
sub s4,s4,s5 #ѭ�������ݼ�
bne s4, zero, IntLoop3
################# ���ж�
csrrci zero,0x4,1 #ustatus.MIE=0
############### ����ָ�� ����(SLL/SB/BLTU ֮һ) ###############
addi s1,zero,-15
bltu_branch:
add a0,zero,s1
addi a7,zero,34
ecall
addi s1,s1,1
bltu zero,s1,bltu_branch
add a0,zero,s1
addi a7,zero,34
ecall
addi sp,sp,-4
lw s2,0(sp)
addi sp,sp,-4
lw s1,0(sp)
addi sp,sp,-4
lw t6,0(sp)
addi sp,sp,-4
lw t5,0(sp)
addi sp,sp,-4
lw t4,0(sp)
addi sp,sp,-4
lw t3,0(sp)
addi sp,sp,-4
lw t2,0(sp)
addi sp,sp,-4
lw t1,0(sp)
addi sp,sp,-4
lw t0,0(sp)
################# �ָ��ֳ�
addi sp, sp, -4
lw s6, 0(sp)
csrrw zero,0x41,s6 #uepc=s6
addi sp, sp, -4
lw s6, 0(sp)
addi sp, sp, -4
lw s5, 0(sp)
addi sp, sp, -4
lw s4, 0(sp)
addi sp, sp, -4
lw s3, 0(sp)
addi sp, sp, -4
lw s0, 0(sp)
addi sp, sp, -4
lw a0, 0(sp)
addi sp, sp, -4
lw a7, 0(sp)
################ �жϷ���
uret #ͬ�����жϣ�uepc-->pc
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