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Anccend/risc-v-cpu
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Anccend 03ac91bf65 初版,Logisim转换Verilog
2026-09-12 13:18:24 +08:00
testbench
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.gitignore
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cpu21_riscv_redirect_int_bpb.v
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cpu21_riscv_redirect_int_bpb说明.md
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2026-09-12 13:18:24 +08:00
真值表.txt
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2026-09-12 13:18:24 +08:00
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Description
26华科硬件综合训练
1.7 MiB
Languages
Verilog 70.7%
Assembly 29.3%
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