Anccend
556fbe9530
- rtl/：12 个可综合的处理器源文件（顶层 cpu21_riscv_redirect_int_bpb.v，其余为各功能单元）。 - board/：板级顶层 cpu21_board_top.v、引脚约束 cpu21_board_top.xdc、片内 ROM 初始化 cpu21_board_rom.vh 与短延时版本 cpu21_board_rom_fast.vh。 - testbench/：保留三个测试平台；ROM 镜像统一放到 testbench/rom/，测试程序源码与期望值 仍在 testbench/programs/（其中的 .hex 是 RARS 原始输出，与 rom/ 里改过显示方式的版本 内容不同，两者都保留）。 - 同步更新：两个测试平台的 ROM 探测路径改为 testbench/rom/（并在头注释里补充说明： PowerShell 会把 -generic_top/--testplusarg 参数里的 "=" 拆开、Verilog 字符串中的 路径要用正斜杠）；tools/hex2vh.py 的用法示例指向 board/cpu21_board_top.v； 说明文档新增“目录结构”一节并同步所有路径引用；.gitignore 补充 .Xil/。 - 清理：删除 *.hex.lst 中间文件与空的 .Xil/ 目录。 - 验证：isa_test 24/24、lui_test 4/4、mmio_test 5/5 三项回归通过；两个基线（5560 / 6003 周期）与整理前一致；板级仿真（默认 ROM 首次写入 LED=0001、快速 ROM 跑马灯循环）正常； Vivado 工程源文件路径同步到 rtl/ 与 board/ 后综合通过（LUT 5276、23 个引脚，与整理前 完全一致），因此已有 bit 文件仍然有效。
77 lines
3.2 KiB
Verilog
77 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// 性能计数器：周期数、停顿/气泡数、条件分支跳转数、无条件跳转数，
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// 以及分支预测的成功/失败次数。
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//
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// 这些计数器只影响可观测的统计量，不参与处理器控制，便于在波形中单独
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// 观察流水线效率。
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// -----------------------------------------------------------------------------
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module cpu21_riscv_perf_counters (
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input wire clk,
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input wire reset,
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input wire inc_cycle_i, // 未停机时周期数 +1
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input wire stall_i, // load-use 停顿
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input wire flush_i, // 冲刷年轻指令
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input wire cond_taken_i, // EX 级条件分支实际跳转
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input wire cond_valid_i, // EX 级条件分支有效
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input wire mispredict_i, // EX 级条件分支预测失败
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input wire uncond_i, // EX 级 JAL/JALR
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output wire [15:0] cycle_count_o,
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output wire [15:0] stall_count_o,
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output wire [15:0] bubble_count_o,
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output wire [15:0] conditional_taken_count_o,
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output wire [15:0] unconditional_branch_count_o,
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output wire [15:0] prediction_success_count_o,
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output wire [15:0] prediction_failure_count_o
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);
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reg [15:0] cycle_count_q;
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reg [15:0] stall_count_q;
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reg [15:0] bubble_count_q;
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reg [15:0] conditional_taken_count_q;
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reg [15:0] unconditional_branch_count_q;
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reg [15:0] prediction_success_count_q;
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reg [15:0] prediction_failure_count_q;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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cycle_count_q <= 16'b0;
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stall_count_q <= 16'b0;
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bubble_count_q <= 16'b0;
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conditional_taken_count_q <= 16'b0;
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unconditional_branch_count_q <= 16'b0;
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prediction_success_count_q <= 16'b0;
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prediction_failure_count_q <= 16'b0;
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end else begin
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if (inc_cycle_i) cycle_count_q <= cycle_count_q + 16'd1;
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if (stall_i) begin
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stall_count_q <= stall_count_q + 16'd1;
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bubble_count_q <= bubble_count_q + 16'd1;
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end else if (flush_i) begin
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// 一次冲刷丢弃 IF/ID 两条年轻指令，记两个气泡。
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bubble_count_q <= bubble_count_q + 16'd2;
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end
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if (cond_taken_i) conditional_taken_count_q <= conditional_taken_count_q + 16'd1;
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if (uncond_i) unconditional_branch_count_q <= unconditional_branch_count_q + 16'd1;
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if (cond_valid_i) begin
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if (mispredict_i) prediction_failure_count_q <= prediction_failure_count_q + 16'd1;
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else prediction_success_count_q <= prediction_success_count_q + 16'd1;
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end
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end
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end
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assign cycle_count_o = cycle_count_q;
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assign stall_count_o = stall_count_q;
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assign bubble_count_o = bubble_count_q;
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assign conditional_taken_count_o = conditional_taken_count_q;
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assign unconditional_branch_count_o = unconditional_branch_count_q;
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assign prediction_success_count_o = prediction_success_count_q;
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assign prediction_failure_count_o = prediction_failure_count_q;
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endmodule
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`default_nettype wire
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