- 新增 rtl/cpu21_riscv_muldiv.v:移位迭代的多周期乘除法单元。
* 乘法:32 拍移位加法得到 64 位乘积;有符号变体先取操作数绝对值,迭代结束后
按符号对 64 位乘积取负。
* 除法:32 拍恢复余数法得到商与余数;除零按 RISC-V 约定(商全 1、余数为被除数)。
* 一次乘/除独占 EX 共 34 拍(1 拍装载 + 32 拍迭代 + 1 拍定型):期间 ID/EX 保持、
EX/MEM 插气泡、取指/译码冻结,并屏蔽中断(避免结果未定型就写回 rd)。
- rtl/cpu21_riscv_alu.v:删除组合的 32x32 乘法与除法/取余(原来关键路径约 94 ns、
325 级逻辑、286 个 CARRY4,是 100 MHz 无法收敛的根因)。ALU_MUL/ALU_DIVU 现在
只作为“这是乘除法指令”的标识,结果由顶层从 muldiv 选取(wb_sel=3 取 result2 的
约定保持不变,译码器与写回选择都不用改)。
- rtl/cpu21_riscv_decoder.v:新增 md_op_o(乘除法操作类型),并补上课程真值表里的
divu(funct3=101)——之前这一项译码缺失,会导致 divu 不写 rd。
- rtl/cpu21_riscv_redirect_int_bpb.v:ID/EX 增加 md_op;EX 级停留、结果选择与中断
屏蔽。另外为时序做了三处行为等价的重构(100 MHz 下 WNS 从 -3.54 ns 改善到
-1.10 ns):
* JAL/JALR 的链接地址 PC+4 改在 EX 级预先算好并随流水寄存器传递,去掉
“写回值/前递 → 停机判定 → 流水控制”路径上的两个 32 位加法器;
* ID/EX 的 payload 时钟使能不再依赖冲刷(只有 valid 位受冲刷控制),把
“EX 级组合判决 → 流水寄存器时钟使能”这条最长路径缩到只剩 1 位;
* ex_block_irq 不再包含 ex_redirect_valid / ex_halt_event(它们本身就会让
flush_younger 有效,中断优先时返回地址由 irq_save_pc 正确给出),切断
“分支判决 → 中断控制器 → flush”的绕行路径。
- rtl/cpu21_riscv_hazard_unit.v:停顿条件去掉 flush_younger(冲刷由 valid 位与
PC/IF-ID 的冲刷分支处理,同时发生停顿只会多保持一拍 payload),避免把长路径
引到 payload 的时钟使能上。
- board/cpu21_board_top.v / .xdc:乘除法已不在关键路径上,分频比从 16 降到 2
(50 MHz,周期 20 ns)。实测(xc7a100tcsg324-1):CLK_DIV=1(100 MHz)下
WNS=-1.1 ns,剩余违例路径是 EX 级“分支判决/中断保存 → BPB 更新”,与乘除法无关
(逻辑只占约 3 ns,其余 ~8 ns 是布线);CLK_DIV=2 时 WNS=+5.109 ns,余量约 25%。
- 上板 ROM 按 50 MHz 重新生成(延时计数 0x7A000 ≈ 20 ms/步,快速版 64 次循环),
CPU 时钟比改造前快 8 倍。
- tools/rv_asm.py:支持 divu / remu 助记符。新增 testbench/programs/muldiv_test.asm
与 muldiv_test.expected(13 个用例:mul/mulh/mulhsu/mulhu/divu/remu、负数、
0xffffffff、除零、0x12345678 大数)。
- 验证:muldiv_test 13/13、isa_test 24/24、lui_test 4/4、mmio_test 5/5 全部 PASS;
两个基线(5560 / 6003 周期)与改造前的流水统计一致(差异只来自多周期乘除法带来的
停顿/气泡计数);中断测试仍能正常进入 0x30ac / 0x31e0 / 0x3300 三层嵌套处理程序;
板级仿真:默认 ROM 首次写入 LED=0001、快速 ROM 跑马灯 0001..8000 循环正常。
- 实现结果:synth_design / route_design / write_bitstream 全部完成,
LUT 5400 → 3420(5.39%)、DSP 12 → 0、IOB 23,时钟 6.25 MHz → 50 MHz,
bit 文件已更新。
233 lines
6.4 KiB
Python
233 lines
6.4 KiB
Python
#!/usr/bin/env python3
|
||
"""极简 RISC-V 汇编器:仅支持本项目测试所需的指令子集。
|
||
|
||
用法: python tools/rv_asm.py <input.asm> <output.hex>
|
||
同时生成 <output.hex>.lst 反汇编/编码清单,便于核对。
|
||
支持:add/sub/and/or/xor/sll/srl/sra/slt/sltu、
|
||
mul/mulh/mulhsu/mulhu、
|
||
addi/slti/sltiu/xori/ori/andi、slli/srli/srai、
|
||
lw/sw/sb、beq/bne/blt/bge/bltu/bgeu、lui、jal/jalr、ecall、标签、# 注释
|
||
伪指令:print(= lui t6,LED_ADDR>>12 + sw a0,0(t6),向 MMIO 的 LED 寄存器写入 a0)、
|
||
halt(= addi a7,zero,10 + ecall),各占两个字。
|
||
示例:python tools/rv_asm.py testbench/programs/isa_test.asm out.hex
|
||
"""
|
||
|
||
import re
|
||
import sys
|
||
|
||
REGS = {
|
||
"zero": 0,
|
||
"ra": 1,
|
||
"sp": 2,
|
||
"gp": 3,
|
||
"tp": 4,
|
||
"t0": 5,
|
||
"t1": 6,
|
||
"t2": 7,
|
||
"s0": 8,
|
||
"s1": 9,
|
||
"a0": 10,
|
||
"a1": 11,
|
||
"a2": 12,
|
||
"a3": 13,
|
||
"a4": 14,
|
||
"a5": 15,
|
||
"a6": 16,
|
||
"a7": 17,
|
||
"s2": 18,
|
||
"s3": 19,
|
||
"s4": 20,
|
||
"s5": 21,
|
||
"s6": 22,
|
||
"s7": 23,
|
||
"s8": 24,
|
||
"s9": 25,
|
||
"s10": 26,
|
||
"s11": 27,
|
||
"t3": 28,
|
||
"t4": 29,
|
||
"t5": 30,
|
||
"t6": 31,
|
||
}
|
||
|
||
|
||
def reg(t):
|
||
t = t.strip()
|
||
if t in REGS:
|
||
return REGS[t]
|
||
m = re.fullmatch(r"x(\d+)", t)
|
||
if m:
|
||
return int(m.group(1))
|
||
raise SystemExit("未知寄存器: " + t)
|
||
|
||
|
||
def num(t):
|
||
return int(t.strip(), 0)
|
||
|
||
|
||
def enc_r(f7, rs2, rs1, f3, rd):
|
||
return (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33
|
||
|
||
|
||
def enc_i(imm, rs1, f3, rd, op=0x13):
|
||
return ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | op
|
||
|
||
|
||
def enc_s(imm, rs2, rs1, f3):
|
||
imm &= 0xFFF
|
||
return (
|
||
((imm >> 5) << 25)
|
||
| (rs2 << 20)
|
||
| (rs1 << 15)
|
||
| (f3 << 12)
|
||
| ((imm & 0x1F) << 7)
|
||
| 0x23
|
||
)
|
||
|
||
|
||
def enc_b(imm, rs2, rs1, f3):
|
||
imm &= 0x1FFF
|
||
return (
|
||
(((imm >> 12) & 1) << 31)
|
||
| (((imm >> 5) & 0x3F) << 25)
|
||
| (rs2 << 20)
|
||
| (rs1 << 15)
|
||
| (f3 << 12)
|
||
| (((imm >> 1) & 0xF) << 8)
|
||
| (((imm >> 11) & 1) << 7)
|
||
| 0x63
|
||
)
|
||
|
||
|
||
def enc_u(imm, rd):
|
||
return ((imm & 0xFFFFF) << 12) | (rd << 7) | 0x37
|
||
|
||
|
||
def enc_j(imm, rd):
|
||
imm &= 0x1FFFFF
|
||
return (
|
||
(((imm >> 20) & 1) << 31)
|
||
| (((imm >> 1) & 0x3FF) << 21)
|
||
| (((imm >> 11) & 1) << 20)
|
||
| (((imm >> 12) & 0xFF) << 12)
|
||
| (rd << 7)
|
||
| 0x6F
|
||
)
|
||
|
||
|
||
RTYPE = {
|
||
"add": (0x00, 0),
|
||
"sub": (0x20, 0),
|
||
"sll": (0x00, 1),
|
||
"slt": (0x00, 2),
|
||
"sltu": (0x00, 3),
|
||
"xor": (0x00, 4),
|
||
"srl": (0x00, 5),
|
||
"sra": (0x20, 5),
|
||
"or": (0x00, 6),
|
||
"and": (0x00, 7),
|
||
"mul": (0x01, 0),
|
||
"mulh": (0x01, 1),
|
||
"mulhsu": (0x01, 2),
|
||
"mulhu": (0x01, 3),
|
||
"divu": (0x01, 5),
|
||
"remu": (0x01, 7),
|
||
}
|
||
ITYPE = {"addi": 0, "slti": 2, "sltiu": 3, "xori": 4, "ori": 6, "andi": 7}
|
||
SHIFT = {"slli": 1, "srli": 5, "srai": 5}
|
||
BTYPE = {"beq": 0, "bne": 1, "blt": 4, "bge": 5, "bltu": 6, "bgeu": 7}
|
||
# MMIO:LED 数据寄存器地址,需与 RTL 顶层 parameter LED_ADDR 保持一致
|
||
LED_ADDR = 0x1000
|
||
|
||
# 双字伪指令:print 向 MMIO 的 LED 写寄存器写入 a0;halt 停机
|
||
PSEUDO_SIZE = {"print": 2, "halt": 2}
|
||
|
||
|
||
def assemble(lines):
|
||
labels, items, addr = {}, [], 0
|
||
for raw in lines:
|
||
line = raw.split("#")[0].strip()
|
||
if not line:
|
||
continue
|
||
while True:
|
||
m = re.match(r"^([A-Za-z_.$][\w.$]*)\s*:\s*(.*)$", line)
|
||
if not m:
|
||
break
|
||
labels[m.group(1)] = addr
|
||
line = m.group(2).strip()
|
||
if not line:
|
||
break
|
||
if not line:
|
||
continue
|
||
items.append((addr, line))
|
||
addr += 4 * PSEUDO_SIZE.get(line.split()[0].lower(), 1)
|
||
|
||
out = []
|
||
for addr, line in items:
|
||
parts = re.split(r"[\s,]+", line)
|
||
mn, a = parts[0].lower(), parts[1:]
|
||
if mn in RTYPE:
|
||
f7, f3 = RTYPE[mn]
|
||
w = enc_r(f7, reg(a[2]), reg(a[1]), f3, reg(a[0]))
|
||
elif mn in ITYPE:
|
||
im = num(a[2])
|
||
if not (-2048 <= im <= 2047):
|
||
raise SystemExit("I 型立即数超出 12 位有符号范围: " + line)
|
||
w = enc_i(im, reg(a[1]), ITYPE[mn], reg(a[0]))
|
||
elif mn in SHIFT:
|
||
w = enc_i(num(a[2]) & 0x1F, reg(a[1]), SHIFT[mn], reg(a[0]))
|
||
elif mn == "lui":
|
||
w = enc_u(num(a[1]), reg(a[0]))
|
||
elif mn in ("lw", "sw", "sb"):
|
||
m = re.fullmatch(r"(-?\w+)\((\w+)\)", a[1])
|
||
if not m:
|
||
raise SystemExit("内存操作数格式应为 imm(rs1): " + line)
|
||
im = num(m.group(1))
|
||
if not (-2048 <= im <= 2047):
|
||
raise SystemExit("访存偏移超出 12 位有符号范围: " + line)
|
||
if mn == "lw":
|
||
w = enc_i(im, reg(m.group(2)), 2, reg(a[0]), 0x03)
|
||
elif mn == "sw":
|
||
w = enc_s(im, reg(a[0]), reg(m.group(2)), 2)
|
||
else: # sb
|
||
w = enc_s(im, reg(a[0]), reg(m.group(2)), 0)
|
||
elif mn in BTYPE:
|
||
tgt = labels[a[2]] if a[2] in labels else num(a[2])
|
||
w = enc_b(tgt - addr, reg(a[1]), reg(a[0]), BTYPE[mn])
|
||
elif mn == "jal":
|
||
tgt = labels[a[1]] if a[1] in labels else num(a[1])
|
||
w = enc_j(tgt - addr, reg(a[0]))
|
||
elif mn == "jalr":
|
||
w = enc_i(num(a[2]), reg(a[1]), 0, reg(a[0]), 0x67)
|
||
elif mn == "ecall":
|
||
w = 0x00000073
|
||
elif mn == "print":
|
||
# 写 MMIO 的 LED 寄存器:lui t6, LED_ADDR>>12 ; sw a0, 0(t6)
|
||
w = [
|
||
enc_u(LED_ADDR >> 12, reg("t6")),
|
||
enc_s(0, reg("a0"), reg("t6"), 2),
|
||
]
|
||
elif mn == "halt":
|
||
w = [enc_i(10, 0, 0, 17), 0x00000073]
|
||
else:
|
||
raise SystemExit("未知助记符: " + mn)
|
||
out.append((addr, line, w if isinstance(w, list) else [w]))
|
||
return out
|
||
|
||
|
||
def main():
|
||
src, dst = sys.argv[1], sys.argv[2]
|
||
with open(src, encoding="utf-8-sig") as f: # 兼容带/不带 BOM
|
||
prog = assemble(f.readlines())
|
||
with open(dst, "w", encoding="ascii") as f:
|
||
for _, _, ws in prog:
|
||
for w in ws:
|
||
f.write("%08X\n" % w)
|
||
with open(dst + ".lst", "w", encoding="utf-8") as f:
|
||
for addr, line, ws in prog:
|
||
f.write("%04X: %s %s\n" % (addr, " ".join("%08X" % w for w in ws), line))
|
||
print("已生成 %s(%d 个字)" % (dst, sum(len(ws) for _, _, ws in prog)))
|
||
|
||
|
||
main()
|