Anccend
036a57d907
- cpu21_riscv_alu.v：新增 ALU_PASSB(4'd15)，直接把 B 端送到 result；
- cpu21_riscv_decoder.v：新增 OP_LUI（IR[6:2]=0x0d，即标准 RISC-V opcode 0x37），
imm = {IR[31:12], 12'b0}，用 ALU_SRC 选择立即数、ALU 直通输出写回 rd，
不读源寄存器（uses_rs1/rs2 保持 0）；
- 说明文档补充 lui 的功能说明与编码表行。
验证（xsim + tb_no_intr，自编的小汇编器生成测试程序）：
依次输出 12345000 / fffff000 / 80000000，以及 lui+addi 组合得到 12345678，
随后 a7=10 停机（共 21 周期，halted=1），无编译错误与警告。
262 lines
8.8 KiB
Verilog
262 lines
8.8 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// ID 级组合译码器。
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//
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// 与原始 Logisim 控制器一致：操作码取标准 RISC-V 的 IR[6:2] 五位字段，
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// 真值表中以十六进制形式存储该字段。
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// 所有输出在无匹配时保持"无操作/不写回"的默认值。
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// -----------------------------------------------------------------------------
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module cpu21_riscv_decoder (
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input wire [31:0] ir_i,
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output reg [ 4:0] rs1_idx_o,
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output reg [ 4:0] rs2_idx_o,
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output reg [ 4:0] rd_o,
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output reg [31:0] imm_o,
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output reg [ 3:0] alu_op_o,
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output reg [ 2:0] wb_sel_o,
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output wire [11:0] csr_addr_o,
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output reg uses_rs1_o,
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output reg uses_rs2_o,
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output reg reg_write_o,
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output reg mem_to_reg_o,
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output reg mem_write_o,
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output reg mem_byte_o,
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output reg alu_src_o,
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output reg branch_o,
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output reg beq_o,
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output reg bne_o,
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output reg blt_o,
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output reg bltu_o,
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output reg jal_o,
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output reg jalr_o,
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output reg ecall_o,
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output reg uret_o,
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output reg csr_set_o,
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output reg csr_clear_o,
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output reg csr_write_o
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);
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// CPU21 自定义操作码（取自所提供的真值表）。
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localparam OP_LOAD = 5'h00;
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localparam OP_R = 5'h0c;
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localparam OP_I = 5'h04;
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localparam OP_STORE = 5'h08;
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localparam OP_JALR = 5'h19;
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localparam OP_BRANCH = 5'h18;
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localparam OP_JAL = 5'h1b;
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localparam OP_SYS = 5'h1c;
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// LUI 为扩展指令（标准 RISC-V opcode 0x37 -> IR[6:2]=0x0d）。
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localparam OP_LUI = 5'h0d;
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localparam ALU_SLL = 4'd0;
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localparam ALU_SRA = 4'd1;
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localparam ALU_SRL = 4'd2;
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localparam ALU_MUL = 4'd3;
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localparam ALU_DIVU = 4'd4;
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localparam ALU_ADD = 4'd5;
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localparam ALU_SUB = 4'd6;
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localparam ALU_AND = 4'd7;
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localparam ALU_OR = 4'd8;
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localparam ALU_XOR = 4'd9;
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localparam ALU_SLT = 4'd11;
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localparam ALU_SLTU = 4'd12;
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localparam ALU_PASSB = 4'd15; // LUI：直接输出 B 端（立即数）
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wire [4:0] opcode = ir_i[6:2];
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wire [2:0] funct3 = ir_i[14:12];
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wire [6:0] funct7 = ir_i[31:25];
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// CSR 地址字段在译码时直接旁路输出（供 EX 级读取 CSR）。
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assign csr_addr_o = ir_i[31:20];
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// 默认控制信号：全部为"无操作/不写回"，再由下面的 case 覆盖。
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always @* begin
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rs1_idx_o = ir_i[19:15];
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rs2_idx_o = ir_i[24:20];
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rd_o = ir_i[11:7];
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imm_o = {{20{ir_i[31]}}, ir_i[31:20]};
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alu_op_o = ALU_ADD;
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wb_sel_o = 3'd0;
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uses_rs1_o = 1'b0;
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uses_rs2_o = 1'b0;
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reg_write_o = 1'b0;
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mem_to_reg_o = 1'b0;
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mem_write_o = 1'b0;
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mem_byte_o = 1'b0;
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alu_src_o = 1'b0;
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branch_o = 1'b0;
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beq_o = 1'b0;
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bne_o = 1'b0;
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blt_o = 1'b0;
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bltu_o = 1'b0;
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jal_o = 1'b0;
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jalr_o = 1'b0;
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ecall_o = 1'b0;
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uret_o = 1'b0;
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csr_set_o = 1'b0;
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csr_clear_o = 1'b0;
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csr_write_o = 1'b0;
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case (opcode)
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// R 型运算：由 funct3/funct7 决定具体操作。
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OP_R: begin
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uses_rs1_o = 1'b1;
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uses_rs2_o = 1'b1;
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reg_write_o = 1'b1;
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// 电路中额外的 REMU 控制对应标准 R 型的 funct7=1/funct3=111
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// 形式；此时 ALU 的 result2 即为余数。
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if ((funct7 == 7'b0000001) && (funct3 == 3'b111)) begin
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alu_op_o = ALU_DIVU;
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wb_sel_o = 3'd3;
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end else if ((funct7 == 7'b0000001) && (funct3 == 3'b000)) begin
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alu_op_o = ALU_MUL;
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end else begin
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// 标准 R 型 funct3 译码；add/sub 与 sra/srl 由 funct7[5] 区分。
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case (funct3)
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3'b000: alu_op_o = (funct7[5] ? ALU_SUB : ALU_ADD);
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3'b001: alu_op_o = ALU_SLL;
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3'b010: alu_op_o = ALU_SLT;
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3'b011: alu_op_o = ALU_SLTU;
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3'b100: alu_op_o = ALU_XOR;
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3'b101: alu_op_o = (funct7[5] ? ALU_SRA : ALU_SRL);
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3'b110: alu_op_o = ALU_OR;
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3'b111: alu_op_o = ALU_AND;
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default: reg_write_o = 1'b0;
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endcase
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end
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end
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// I 型运算（addi/slli/slti/xori/srai/srli/ori/andi）。
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OP_I: begin
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uses_rs1_o = 1'b1;
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alu_src_o = 1'b1;
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reg_write_o = 1'b1;
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case (funct3)
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3'b000: alu_op_o = ALU_ADD; // addi：立即数加
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3'b001: alu_op_o = ALU_SLL; // slli：立即数逻辑左移
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3'b010: alu_op_o = ALU_SLT; // slti：有符号小于置 1
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3'b100: alu_op_o = ALU_XOR; // xori：立即数异或
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3'b101:
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alu_op_o = (funct7[5] ? ALU_SRA : ALU_SRL); // srai/srli：立即数算术/逻辑右移
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3'b110: alu_op_o = ALU_OR; // ori：立即数或
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3'b111: alu_op_o = ALU_AND; // andi：立即数与
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default: reg_write_o = 1'b0;
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endcase
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end
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// 加载高位立即数 lui：rd = imm[31:12] << 12。
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// 不读寄存器；用 ALU_SRC 选立即数，ALU 直通 B 端输出。
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OP_LUI: begin
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reg_write_o = 1'b1;
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alu_src_o = 1'b1;
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alu_op_o = ALU_PASSB;
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imm_o = {ir_i[31:12], 12'b0};
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wb_sel_o = 3'd0;
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end
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// 加载指令，当前仅支持 lw（funct3=010）。
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OP_LOAD: begin
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if (funct3 == 3'b010) begin
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uses_rs1_o = 1'b1;
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alu_src_o = 1'b1;
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alu_op_o = ALU_ADD;
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mem_to_reg_o = 1'b1;
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reg_write_o = 1'b1;
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wb_sel_o = 3'd1;
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end
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end
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// 存储指令：sw（funct3=010）与 sb（funct3=000）。
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OP_STORE: begin
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if ((funct3 == 3'b010) || (funct3 == 3'b000)) begin
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uses_rs1_o = 1'b1;
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uses_rs2_o = 1'b1;
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alu_src_o = 1'b1;
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alu_op_o = ALU_ADD;
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mem_write_o = 1'b1;
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mem_byte_o = (funct3 == 3'b000); // sb：字节存储
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imm_o = {{20{ir_i[31]}}, ir_i[31:25], ir_i[11:7]};
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end
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end
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// 条件分支：beq（000）/bne（001）/blt（100，有符号小于）/bltu（110，无符号小于）。
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OP_BRANCH: begin
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if ((funct3 == 3'b000) || (funct3 == 3'b001) ||
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(funct3 == 3'b100) || (funct3 == 3'b110)) begin
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uses_rs1_o = 1'b1;
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uses_rs2_o = 1'b1;
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branch_o = 1'b1;
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beq_o = (funct3 == 3'b000);
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bne_o = (funct3 == 3'b001);
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blt_o = (funct3 == 3'b100);
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bltu_o = (funct3 == 3'b110);
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// 真值表：beq/bne 用减法比较，blt 用 ALU_SLT，bltu 用 ALU_SLTU。
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alu_op_o = blt_o ? ALU_SLT : (bltu_o ? ALU_SLTU : ALU_SUB);
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imm_o = {{19{ir_i[31]}}, ir_i[31], ir_i[7], ir_i[30:25], ir_i[11:8], 1'b0};
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end
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end
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// 无条件跳转并链接：jal（写回 PC+4）。
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OP_JAL: begin
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jal_o = 1'b1;
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reg_write_o = 1'b1;
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wb_sel_o = 3'd2;
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imm_o = {{11{ir_i[31]}}, ir_i[31], ir_i[19:12], ir_i[20], ir_i[30:21], 1'b0};
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end
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// 寄存器间接跳转并链接：jalr。
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OP_JALR: begin
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if (funct3 == 3'b000) begin
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jalr_o = 1'b1;
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uses_rs1_o = 1'b1;
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alu_src_o = 1'b1;
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alu_op_o = ALU_ADD;
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reg_write_o = 1'b1;
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wb_sel_o = 3'd2;
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end
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end
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// 系统指令：ecall / uret / CSR 读写。
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OP_SYS: begin
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// 电路用 IR[21] 区分 URET 与 ecall。
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if (funct3 == 3'b000) begin
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if (ir_i[21]) begin
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uret_o = 1'b1;
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end else begin
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ecall_o = 1'b1;
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// 按文档说明，ecall 读取 a7(rs17) 与 a0(rs10)。
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uses_rs1_o = 1'b1;
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uses_rs2_o = 1'b1;
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rs1_idx_o = 5'd17;
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rs2_idx_o = 5'd10;
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end
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end else if (funct3 == 3'b001) begin
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csr_write_o = 1'b1; // CSRRW：写 CSR，并把旧值写回 rd
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uses_rs1_o = 1'b1;
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alu_src_o = 1'b1;
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imm_o = {27'b0, ir_i[19:15]};
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reg_write_o = (rd_o != 5'd0);
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wb_sel_o = 3'd4;
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end else if (funct3 == 3'b110) begin
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csr_set_o = 1'b1; // CSRRSI：置位 CSR 中的指定位
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imm_o = {27'b0, ir_i[19:15]};
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reg_write_o = (rd_o != 5'd0);
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wb_sel_o = 3'd4;
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end else if (funct3 == 3'b111) begin
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csr_clear_o = 1'b1; // CSRRCI：清除 CSR 中的指定位
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imm_o = {27'b0, ir_i[19:15]};
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reg_write_o = (rd_o != 5'd0);
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wb_sel_o = 3'd4;
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end
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end
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default: begin
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end
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endcase
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end
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endmodule
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`default_nettype wire
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