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risc-v-cpu
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Anccend
abb2e161af
注释添加和翻译
2026-09-12 16:34:30 +08:00
testbench
注释添加和翻译
2026-09-12 16:34:30 +08:00
.gitignore
初版,Logisim转换Verilog
2026-09-12 13:18:24 +08:00
cpu21_riscv_redirect_int_bpb.v
注释添加和翻译
2026-09-12 16:34:30 +08:00
cpu21_riscv_redirect_int_bpb说明.md
初版,Logisim转换Verilog
2026-09-12 13:18:24 +08:00
真值表.txt
初版,Logisim转换Verilog
2026-09-12 13:18:24 +08:00
S
Description
26华科硬件综合训练
1.7
MiB
Languages
Verilog
72.4%
Assembly
27.6%