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初版，Logisim转换Verilog

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Anccend
2026-09-12 13:18:24 +08:00
commit 03ac91bf65
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真值表.txt
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# 指令 "Funct7
(十进制)" "Funct3
(十进制)" "OpCode
(十六进制)" ALU_OP MemtoReg MemWrite ALU_Src RegWrite ecall S_Type BEQ BNE Jal jalr REMU sel BLT r1u r2u CSR CSRW CSRRCI
1 add 0 0 C 5 1 1 1
2 sub 32 0 C 6 1 1 1
3 and 0 7 C 7 1 1 1
4 or 0 6 C 8 1 1 1
5 slt 0 2 C 11 1 1 1
6 sltu 0 3 C 12 1 1 1
7 addi 0 4 5 1 1 1
8 andi 7 4 7 1 1 1
9 ori 6 4 8 1 1 1
10 xori 4 4 9 1 1 1
11 slti 2 4 11 1 1 1
12 slli 0 1 4 0 1 1 1
13 srli 0 5 4 2 1 1 1
14 srai 32 5 4 1 1 1 1
15 lw 2 0 5 1 1 1 1
16 sw 2 8 5 1 1 1 1 1
17 ecall 0 0 1C 1 1 1
18 beq 0 18 6 1 1 1
19 bne 1 18 6 1 1 1
20 jal 1B 1 1
21 jalr 0 19 6 1 1 1 1
22 CSRRSI 6 1C 8 1 1 1
23 CSRRCI 7 1C 7 1 1 1 1
24 URET 2 0 1C 1
25 DIVU 1 5 C 4 1 1 1
26 REMU 1 7 C 4 1 1 1 1
27 SB 0 8 5 1 1 1 1 1 1
28 BLT 4 18 11 1 1 1
29 CSRRW 1 1C 1 1 1