Alpha
3f765ae4c5
- cpu21_mmio.v: sel_fb 原写成 addr[12] && !addr[11]（那是 0x1000-0x17FF）， 导致 0x2000+ 的显存读写全不命中, 而鼠标/显示寄存器写反而落进显存。 改为 bit13=1 && bit12=0 && bit11=0 后扫雷画面才正常: 修复前仿真 fb_we 只有 6 次写（画面全空）, 修复后开始界面 1246 次、进关卡后 2775 次 - cpu21_board_top.v: 新增 POINTER_SAMPLE_DIV 参数(默认仍为上板的 50000), 仿真传 50 即可让按键在几十微秒内被识别（defparam 对 generate 块内实例无效） - saolei/tools/elf2hex.py: .text.isr1/2/3 之间的空洞(0 字)填 NOP —— objcopy 留下的 0x00000000 在本 CPU 上等同自跳指令, PC 掉进去就出不来 - saolei/tools/fb2png.py + srcs/tb/tb_saolei.v: 无 VGA 显示器的调试台 —— 跑板级顶层、 按键当鼠标、把 40x30 显存 dump 成文本, 再按 cpu21_vga.v 的字库/调色板还原 PNG, 并附 ASCII 图 + RAM 变量视图 + PC 热点直方图
313 lines
13 KiB
Verilog
313 lines
13 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// MMIO：把外设寄存器映射到数据存储器地址空间。
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//
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// 地址映射（字节地址，都是"字对齐"译码：同一 32 位寄存器内的任意字节偏移都命中，
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// 具体改哪几个字节由 wstrb_i 决定，与原来 LED 的语义一致）：
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//
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// 0x0000_1000 LED 数据寄存器（**保持原有语义不变**，led_valid_o 拉高一拍）
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// 0x0000_1004 七段数码管：8 位十六进制数（每 4 位一个数码管，低 4 位 = 最右）
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// 0x0000_1100 + 4*k 鼠标寄存器组（见下）
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// 0x0000_1140 + 4*k 显示控制器寄存器（见下）
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// 0x0000_2000 - 0x27FF 显存窗口：40x30 格、每格 1 字节（只用到前 1200 字节）
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//
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// 鼠标寄存器（基址 0x1100）：
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// +0x00 STATUS RO [0] FIFO 非空 [5:1] 项数 [6] 中断使能 [7] FIFO 满
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// +0x04 DATA RO [7:0] dx [15:8] dy [20:16] 按键（读无副作用）
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// +0x08 ACK WO 写任意值 -> 弹出 FIFO 一项
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// +0x0C CTRL RW [0] 中断使能（复位默认 1）
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// +0x10 INPUT RO [15:0] 拨码开关 [20:16] 按键（原样）
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// +0x14 TIME RO 自由运行计数器（随机种子）
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// +0x18 FRAME RO VGA 帧计数
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// +0x1C EVCNT RO 累计鼠标事件数
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// +0x20 LEVEL RW [0] 写 1 -> 拉起 level_irq_o（软件中断，用作"关卡入口"）；
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// 关卡程序返回前要写 0 清掉，否则下次没有上升沿
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// +0x24 MAGIC RO 0xCAFE0002（自检用：读得到说明 MMIO 活着）
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//
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// 显示控制器寄存器（基址 0x1140）：
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// +0x00 CTRL RW [0] 光标可见 [6:4] 背景色（3 位调色板）
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// +0x04 CURSOR RW [5:0] 列(0..39) [13:8] 行(0..29)
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// +0x08 MAGIC RO 0xCAFE0001
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//
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// 显存本体不在本模块里：写操作通过 fb_* 端口直接送到板级顶层的双口 RAM（VGA 读
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// 同一块 RAM），读操作把 fb_rdata_i 组合回读数据，保持"组合读"的时序不变。
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//
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// 两个中断源：
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// mouse_irq_o = 中断使能 && 事件 FIFO 非空（接 irq_i[0]）
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// level_irq_o = LEVEL 寄存器（软件中断，接 irq_i[1]，用来"进入关卡"）
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//
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// 以后要增加外设（UART、SD 卡等）时只需在这里扩展地址译码。
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// -----------------------------------------------------------------------------
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module cpu21_mmio #(
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parameter [31:0] LED_ADDR = 32'h0000_1000,
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parameter integer FB_WORDS = 300,
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parameter integer FIFO_DEPTH = 16
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) (
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input wire clk,
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input wire reset,
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// MEM 级的访存请求（来自 EX/MEM 流水寄存器）
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input wire mem_valid_i,
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input wire mem_write_i,
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input wire mem_read_i,
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input wire [31:0] addr_i,
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input wire [31:0] wdata_i,
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input wire [ 3:0] wstrb_i,
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// MMIO 读回
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output wire [31:0] rdata_o,
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output wire rdata_hit_o,
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// LED 外设（原样保留）
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output reg [31:0] led_data_o,
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output reg led_valid_o,
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// 七段数码管：8 位十六进制数
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output reg [31:0] seg_data_o,
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output reg seg_valid_o,
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// 显存写端口（板级顶层的双口 RAM）
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output wire fb_we_o,
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output wire [ 9:0] fb_waddr_o,
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output wire [31:0] fb_wdata_o,
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output wire [ 3:0] fb_wstrb_o,
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input wire [31:0] fb_rdata_i,
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// 显示控制器寄存器（给 VGA 用）
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output wire [31:0] disp_ctrl_o,
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output wire [31:0] disp_cursor_o,
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// 鼠标事件源（来自板级顶层：按键去抖 / PS/2 解析）
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input wire mouse_ev_valid_i,
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input wire [ 7:0] mouse_dx_i,
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input wire [ 7:0] mouse_dy_i,
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input wire [ 4:0] mouse_btn_i,
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input wire [15:0] sw_i,
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input wire frame_tick_i,
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// 中断
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output wire mouse_irq_o,
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output wire level_irq_o
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);
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// ---------------------------------------------------------------------------
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// 地址译码（都按"字"对齐：同一 32 位寄存器内的任意字节偏移都算命中）
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// ---------------------------------------------------------------------------
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localparam [31:0] SEG_ADDR = 32'h0000_1004;
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localparam [31:0] MOUSE_BASE = 32'h0000_1100;
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localparam [31:0] DISP_BASE = 32'h0000_1140;
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localparam integer FIFO_AW = 4;
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localparam [FIFO_AW:0] FIFO_FULL_V = FIFO_DEPTH[FIFO_AW:0];
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wire sel_led = (addr_i[31:2] == LED_ADDR[31:2]);
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wire sel_seg = (addr_i[31:2] == SEG_ADDR[31:2]);
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wire sel_mouse = (addr_i[31:8] == MOUSE_BASE[31:8]) && (addr_i[7:6] == 2'b00);
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wire sel_disp = (addr_i[31:8] == DISP_BASE[31:8]) && (addr_i[7:6] == 2'b01);
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// 显存窗口 0x2000 - 0x27FF：bit13=1、bit12=0、bit11=0，高位全 0
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// （原来写成 addr[12] && !addr[11]，要求 bit12=1 —— 那是 0x1000-0x17FF，
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// 于是 0x2000+ 的读写全都不命中、而鼠标/显示寄存器写反而落进了显存）
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wire sel_fb = (addr_i[31:14] == 18'd0) && addr_i[13] && !addr_i[12] && !addr_i[11];
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wire [3:0] midx = addr_i[5:2];
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wire [3:0] didx = addr_i[5:2];
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wire [9:0] fb_widx = addr_i[10:2];
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wire fb_ok = (fb_widx < FB_WORDS);
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wire led_wr = mem_valid_i && mem_write_i && sel_led;
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wire led_rd = mem_valid_i && mem_read_i && sel_led;
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wire seg_wr = mem_valid_i && mem_write_i && sel_seg;
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wire seg_rd = mem_valid_i && mem_read_i && sel_seg;
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wire mo_wr = mem_valid_i && mem_write_i && sel_mouse;
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wire mo_rd = mem_valid_i && mem_read_i && sel_mouse;
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wire dp_wr = mem_valid_i && mem_write_i && sel_disp;
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wire dp_rd = mem_valid_i && mem_read_i && sel_disp;
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wire fb_wr = mem_valid_i && mem_write_i && sel_fb && fb_ok;
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wire fb_rd = mem_valid_i && mem_read_i && sel_fb && fb_ok;
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assign fb_we_o = fb_wr;
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assign fb_waddr_o = fb_widx;
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assign fb_wdata_o = wdata_i;
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assign fb_wstrb_o = wstrb_i;
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assign rdata_hit_o = led_rd | seg_rd | mo_rd | dp_rd | fb_rd;
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// 字节写合并：sw 改 4 字节、sb 只改 1 字节（与 RAM 的字节写语义一致）
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function [31:0] merge_bytes;
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input [31:0] new_v;
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input [31:0] old_v;
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input [ 3:0] strb;
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begin
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merge_bytes[7:0] = strb[0] ? new_v[7:0] : old_v[7:0];
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merge_bytes[15:8] = strb[1] ? new_v[15:8] : old_v[15:8];
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merge_bytes[23:16] = strb[2] ? new_v[23:16] : old_v[23:16];
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merge_bytes[31:24] = strb[3] ? new_v[31:24] : old_v[31:24];
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end
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endfunction
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// ---------------------------------------------------------------------------
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// LED：保持原有语义（led_valid_o 只拉高一拍）
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// ---------------------------------------------------------------------------
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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led_data_o <= 32'b0;
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led_valid_o <= 1'b0;
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end
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else begin
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led_valid_o <= 1'b0;
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if (led_wr) begin
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led_data_o <= merge_bytes(wdata_i, led_data_o, wstrb_i);
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led_valid_o <= 1'b1;
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end
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end
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end
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// ---------------------------------------------------------------------------
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// 七段数码管：8 位十六进制数（低 4 位 = 最右边那个数码管）
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// ---------------------------------------------------------------------------
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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seg_data_o <= 32'b0;
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seg_valid_o <= 1'b0;
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end
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else begin
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seg_valid_o <= 1'b0;
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if (seg_wr) begin
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seg_data_o <= merge_bytes(wdata_i, seg_data_o, wstrb_i);
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seg_valid_o <= 1'b1;
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end
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end
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end
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// ---------------------------------------------------------------------------
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// 显示控制器寄存器（显存本体在板级顶层）
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// ---------------------------------------------------------------------------
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reg [31:0] disp_ctrl_q, disp_cursor_q;
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assign disp_ctrl_o = disp_ctrl_q;
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assign disp_cursor_o = disp_cursor_q;
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// ---------------------------------------------------------------------------
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// 鼠标：事件 FIFO + 寄存器 + 中断
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// ---------------------------------------------------------------------------
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reg [31:0] fifo [0:FIFO_DEPTH-1];
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reg [FIFO_AW-1:0] wr_ptr_q, rd_ptr_q;
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reg [FIFO_AW:0] cnt_q;
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reg [31:0] mctrl_q, time_q, frame_q, evcnt_q;
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reg level_q;
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wire fifo_empty = (cnt_q == {FIFO_AW+1{1'b0}});
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wire fifo_full = (cnt_q == FIFO_FULL_V);
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wire [31:0] fifo_head = fifo[rd_ptr_q];
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wire irq_en = mctrl_q[0];
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assign mouse_irq_o = irq_en && !fifo_empty;
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assign level_irq_o = level_q;
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wire push = mouse_ev_valid_i && !fifo_full;
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wire pop = mo_wr && (midx == 4'd2) && !fifo_empty;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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mctrl_q <= 32'h0000_0001; // 鼠标中断默认打开
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time_q <= 32'd0;
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frame_q <= 32'd0;
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evcnt_q <= 32'd0;
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level_q <= 1'b0;
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wr_ptr_q <= {FIFO_AW{1'b0}};
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rd_ptr_q <= {FIFO_AW{1'b0}};
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cnt_q <= {(FIFO_AW+1){1'b0}};
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disp_ctrl_q <= 32'h0000_0001; // 光标可见，背景色 0
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disp_cursor_q <= 32'h0000_0000;
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end
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else begin
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time_q <= time_q + 32'd1;
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if (frame_tick_i)
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frame_q <= frame_q + 32'd1;
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if (push) begin
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fifo[wr_ptr_q] <= {11'b0, mouse_btn_i, mouse_dy_i, mouse_dx_i};
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wr_ptr_q <= wr_ptr_q + 1'b1;
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evcnt_q <= evcnt_q + 32'd1;
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end
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if (pop)
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rd_ptr_q <= rd_ptr_q + 1'b1;
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cnt_q <= cnt_q + (push ? 1'b1 : 1'b0) - (pop ? 1'b1 : 1'b0);
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// 鼠标寄存器：CTRL(3) / LEVEL(8)
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if (mo_wr) begin
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case (midx)
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4'd3:
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mctrl_q <= merge_bytes(wdata_i, mctrl_q, wstrb_i);
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4'd8:
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level_q <= wdata_i[0];
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default:
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;
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endcase
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end
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// 显示控制器：CTRL(0) / CURSOR(1)
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if (dp_wr) begin
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case (didx)
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4'd0:
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disp_ctrl_q <= merge_bytes(wdata_i, disp_ctrl_q, wstrb_i);
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4'd1:
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disp_cursor_q <= merge_bytes(wdata_i, disp_cursor_q, wstrb_i);
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default:
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;
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endcase
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end
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end
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end
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// ---------------------------------------------------------------------------
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// 读数据（组合，与"指令存储器组合读/数据存储器组合读"的时序一致）
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// ---------------------------------------------------------------------------
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reg [31:0] rdata_mux;
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always @* begin
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rdata_mux = 32'b0;
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if (led_rd) begin
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rdata_mux = led_data_o;
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end
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else if (seg_rd) begin
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rdata_mux = seg_data_o;
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end
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else if (fb_rd) begin
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rdata_mux = fb_rdata_i;
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end
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else if (mo_rd) begin
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case (midx)
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4'd0:
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rdata_mux = {24'b0, fifo_full, irq_en, cnt_q[4:0], !fifo_empty};
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4'd1:
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rdata_mux = fifo_head;
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4'd3:
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rdata_mux = mctrl_q;
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4'd4:
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rdata_mux = {11'b0, mouse_btn_i, sw_i};
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4'd5:
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rdata_mux = time_q;
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4'd6:
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rdata_mux = frame_q;
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4'd7:
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rdata_mux = evcnt_q;
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4'd8:
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rdata_mux = {31'b0, level_q};
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4'd9:
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rdata_mux = 32'hCAFE_0002;
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default:
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rdata_mux = 32'b0;
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endcase
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end
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else if (dp_rd) begin
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case (didx)
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4'd0:
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rdata_mux = disp_ctrl_q;
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4'd1:
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rdata_mux = disp_cursor_q;
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4'd2:
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rdata_mux = 32'hCAFE_0001;
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default:
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rdata_mux = 32'b0;
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endcase
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end
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end
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assign rdata_o = rdata_mux;
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endmodule
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`default_nettype wire
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