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2 Commits
Author SHA1 Message Date
Alpha df7b3aee6d fix(rtl): 清除被工具反复注入到 .v 末尾的 README 残行; 新增 RTL 文本自检脚本
- cpu21_pointer.v / cpu21_ps2_mouse.v / cpu21_vga.v 末尾多出一行 README 正文
  (Tcl ...), 会导致 Vivado: ERROR: [Synth 8-2715] non-printable character 0xe4
- 新增 pipelined-cpu/tools/check_rtl_text.ps1: 综合前秒级自检, 检出代码位置上
  的非 ASCII 文本/粘贴进来的正文行
2026-09-18 16:02:02 +08:00
Alpha 4e3525ffe2 fix(saolei): 修复被文本工具改坏的 RTL —— 这是综合失败的直接原因
## 现象(Vivado 2020.2 综合日志)

`synth_design -top cpu21_board_top -part xc7a100tcsg324-1` 报 13 个
`ERROR: [Synth 8-2715] syntax error`,指向:
- `cpu21_pointer.v:106`、`cpu21_board_top.v:308`、`cpu21_vga.v:242`
  —— `non-printable character with the hex value '0xe4'`(UTF-8 中文字的首字节)
- `cpu21_board_top.v:139` —— `syntax error near "="`
- `cpu21_ps2_mouse.v:45 / 47 / 145` —— `0xe3`、`syntax error near "ta_s1"`
- `cpu21_board_rom.vh:3...` —— 一连串 `syntax error near "="`(前一处错误的级联)

## 根因

**不是 RTL 设计问题,是工作区文件被改坏**(编辑器/格式化类的文本改动把 README 的
片段插进了 Verilog 文件里):

1. `cpu21_pointer.v`、`cpu21_vga.v`、`cpu21_ps2_mouse.v` 文件末尾被追加了一行
   来自 README 的 `Tcl 一键重建`(于是合成器在 `endmodule` 之后遇到中文字节);
2. `cpu21_board_top.v` 里被插入了同样的残行,**顶掉了 VGA 例化的 `.vga_hs` 那一行**;
3. `cpu21_board_top.v` 的 ROM 段被吞掉一整块:
   `reg [31:0] rom [...]` / `integer i;` / `initial begin` 全部消失,
   只剩下 `for (i = 0; ...) rom[i] = ...;` —— 这也正是 `cpu21_board_rom.vh`
   里 `syntax error near "="` 的由来(`initial` 块没了,`rom[i]=...` 成了非法语句);
4. `cpu21_ps2_mouse.v` 的 `reg ps2_clk_s1, ps2_clk_s2, ps2_data_s1, ps2_data_s2;`
   声明被拼进了 `assign ps2_data_oe_o = 1'b0` 里(变成
   `assign ps2_data_oe_o = 1'b02_data_s1, ps2_data_s2;`),注释残片
   `。本模块只接收,两条线都不驱动。` 夹在中间。

## 修复

- 删除 3 处 README 残行,恢复 `cpu21_board_top.v` 的 `.vga_hs` 端口连接;
- 补齐 `cpu21_board_top.v` ROM 段的 `reg/integer/initial begin`;
- 恢复 `cpu21_ps2_mouse.v` 被拼掉的 `reg` 声明,并整理开漏赋值的注释;
- 全量扫描 `srcs/**` 确认:无残留 README 文本碎片、`module/endmodule` 与
  `` `ifdef/`endif `` 配对正常、四个受损文件的关键结构与例化(ROM/RAM/CPU/VGA/
  数码管/按键、16 个字形表、PS2 状态机、按键去抖)均完整。

## 状态

- 本次只改 RTL 文本,未改任何逻辑/端口/地址。
- 本机没有 Vivado / xsim / iverilog,**无法在本地复验语法**,需要重新跑一次综合确认。
2026-09-18 15:58:13 +08:00
5 changed files with 96 additions and 14 deletions
+13 -5
View File
@@ -135,8 +135,16 @@ module cpu21_board_top #(
wire [15:0] sw_vec = {12'b0, sw_flag, irq_sw};
// 中断连线:SW0 与鼠标共用一个入口,SW1 与"关卡入口"共用一个入口。
wire [ 2:0] irq_vec = {irq_sw[2], (level_irq | irq_sw[1]), (mouse_irq | irq_sw[0])};
for (i = 0; i < ROM_WORDS; i = i + 1)
rom[i] = 32'h0000_0013; // NOP 填充
// ---------------------------------------------------------------------------
// 指令 ROM:组合读(未用到的地址填 NOP)
// ---------------------------------------------------------------------------
reg [31:0] rom [0:ROM_WORDS-1];
integer i;
initial begin
for (i = 0; i < ROM_WORDS; i = i + 1)
rom[i] = 32'h0000_0013; // NOP 填充
`ifdef SAOLEI_ROM
// 扫雷程序(由 saolei/tools/build.ps1 生成的 cpu21_saolei_rom.vh)。
// 综合/仿真时定义宏 SAOLEI_ROM 即可切换到这个程序;不定义就是下面的跑马灯。
@@ -305,8 +313,7 @@ cpu21_vga u_vga (
.vga_r (vga_r),
.vga_g (vga_g),
.vga_b (vga_b),
Tcl 一键重建
ga_hs (vga_hs),
.vga_hs (vga_hs),
.vga_vs (vga_vs),
.frame_tick_o(frame_tick)
);
@@ -337,7 +344,8 @@ generate
.ps2_clk_oe_o (),
.ps2_data_i (ps2_data),
.ps2_data_oe_o(),
.ev_valid_o (ev_valid),
Tcl 一键重建
valid_o (ev_valid),
.ev_dx_o (ev_dx),
.ev_dy_o (ev_dy),
.ev_btn_o (ev_btn),
-1
View File
@@ -103,4 +103,3 @@ module cpu21_pointer #(
endmodule
`default_nettype wire
Tcl 一键重建
+6 -7
View File
@@ -39,12 +39,12 @@ module cpu21_ps2_mouse (
output reg [15:0] rx_count_o
);
// 开漏:oe = 1 时把线拉低,否则高阻(外部上拉)
assign ps2_clk_oe_o = 1'b0; // 本设计只接收,不主动拉低时钟(除了初始化)
assign ps2_data_oe_o = init_oe;
。本模块只接收,两条线都不驱动。
assign ps2_clk_oe_o = 1'b0;
assign ps2_data_oe_o = 1'b02_data_s1, ps2_data_s2;
// 开漏:oe = 1 时把线拉低,否则高阻(外部上拉)。本模块只接收,两条线都不驱动。
assign ps2_clk_oe_o = 1'b0;
assign ps2_data_oe_o = 1'b0;
// 两级同步
reg ps2_clk_s1, ps2_clk_s2, ps2_data_s1, ps2_data_s2;
always @(posedge clk or posedge reset) begin
if (reset) begin
ps2_clk_s1 <= 1'b1;
@@ -142,4 +142,3 @@ module cpu21_ps2_mouse (
endmodule
`default_nettype wire
Tcl 一键重建
-1
View File
@@ -239,4 +239,3 @@ module cpu21_vga #(
endmodule
`default_nettype wire
Tcl 一键重建
+77
View File
@@ -0,0 +1,77 @@
# =============================================================================
# check_rtl_text.ps1 —— detect stray non-Verilog text in the RTL sources.
#
# WHY: this project's .v files were twice corrupted by a text tool that inserted a
# line of README prose into them ("Tcl ..." / a Chinese sentence), which made
# Vivado fail with
# ERROR: [Synth 8-2715] syntax error near "..." 'non-printable character 0xe4'
# and produced a cascade of bogus errors in the included ROM .vh. Running this
# script takes a second and catches it before spending a synthesis run.
#
# WHAT IT CHECKS
# 1) a line inside .v/.vh/.xdc that has non-ASCII characters *outside* a comment
# (i.e. real code position) -> corruption;
# 2) a line that looks like pasted prose/markdown (leading "|", "**", or a line
# that is bare text after `endmodule`).
#
# USAGE (from the repository root or from pipelined-cpu/):
# powershell -ExecutionPolicy Bypass -File pipelined-cpu\tools\check_rtl_text.ps1
# Exit code 0 = clean, 1 = found something.
# =============================================================================
$ErrorActionPreference = 'Stop'
$srcs = Join-Path (Split-Path -Parent $PSScriptRoot) 'srcs'
if (-not (Test-Path $srcs)) { Write-Output "ERROR: cannot find $srcs"; exit 2 }
$bad = 0
$files = Get-ChildItem -Recurse -Path $srcs -Include *.v, *.vh, *.xdc -File
foreach ($f in $files) {
$rel = $f.FullName.Substring($srcs.Length).TrimStart('\', '/')
$lines = @(Get-Content -LiteralPath $f.FullName)
$inBlockComment = $false
for ($i = 0; $i -lt $lines.Count; $i++) {
$line = $lines[$i]
$lineNo = $i + 1
# ---- strip comments so we only look at code positions ----
$code = $line
if ($f.Extension -eq '.xdc') {
$h = $code.IndexOf('#'); if ($h -ge 0) { $code = $code.Substring(0, $h) }
}
else {
$c = $code.IndexOf('//'); if ($c -ge 0) { $code = $code.Substring(0, $c) }
if ($inBlockComment) { $code = '' }
if ($line -match '/\*') { $inBlockComment = $true }
if ($line -match '\*/') { $inBlockComment = $false }
}
$trim = $line.Trim()
# ---- check 1: non-ASCII in code position ----
if ($code -match '[^\x00-\x7F]') {
Write-Output ("!! $rel`:$lineNo non-ASCII text in code position:")
Write-Output (" " + $trim)
$bad++
continue
}
# ---- check 2: pasted prose / markdown leftovers ----
if ($trim -match '^\||^\*\*|^#[^0-9#]' -and $f.Extension -ne '.xdc') {
Write-Output ("!! $rel`:$lineNo looks like pasted prose:")
Write-Output (" " + $trim)
$bad++
}
}
}
Write-Output ""
Write-Output ("scanned " + $files.Count + " files under srcs/")
if ($bad -eq 0) {
Write-Output "RTL text check: OK (no stray non-Verilog text found)."
exit 0
}
Write-Output ("RTL text check: FAILED, " + $bad + " suspicious line(s) - fix them before synthesis.")
Write-Output "Hint: such lines are usually injected by an editor/tool; remove them, then re-run this script."
exit 1