feat(board): 新增课程新版中断测试上板（多级中断 + 附加 SLL/SB/BLTU）

- programs/risc-v-intrupt-sllsb.asm/.hex: 课程原始程序（344 字，hex 已去掉 Logisim
  的 v2.0 raw 头），保留原文件以便追溯
- tools/adapt_intrupt_sllsb.py: 把它适配到本 CPU 上板（只改 ROM 内容，地址不变）
  - 课程用 addi a7,zero,34 + ecall 显示，本 CPU 里那是空操作 -> 每条显示点原地换成
    一次调用：主程序 jal ra,DISP_DLY；ISR 用 add a7,a0,zero + jal a0,DISP_DLY_ISR
    （三个 ISR 都没保存 ra，所以 ISR 版把链接寄存器放 a0、显示值放 a7）
  - DISP_DLY / DISP_DLY_ISR 各 8 条，追加在 uret 之后，中断入口 0x0AC/0x240/0x3E8 不变
  - 返回地址存 sp+256（越过 ISR 最多 192 字节的栈区），嵌套中断也破坏不了
  - 脚本自带跳转目标自检（曾发现 ISR 侧 jal 偏移少算一条指令的问题）
- srcs/board/cpu21_board_top.v: 新增 RISC_V_INTRUPT_SLLSB_ROM 分支（ROM 选择、
  CPU 分频用 CLK_DIV_INTRUPT、中断向量 0x0AC/0x240/0x3E8）
- srcs/board/risc-v-intrupt-sllsb.vh: 生成的 ROM 初始化（1024 字，程序 360 字）
- create_project.tcl: 新增 use_intrupt_sllsb 开关（默认 1，已把 ccab 置 0）

实测：Vivado 2020.2 建工程 + 综合通过（sources_1 verilog_define =
RISC_V_INTRUPT_SLLSB_ROM，synth_design Complete! 100%）

pipelined-cpu/programs/risc-v-intrupt-sllsb.hex

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