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源文件收敛到 pipelined-cpu/ 一份：删除根目录 rtl/board/testbench/tools，补充回归脚本

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- 现在只有一份源文件，就在 pipelined-cpu/ 下：
    srcs/rtl（13 个处理器 RTL）、srcs/board、srcs/constrs、srcs/tb、srcs/rom、
    tools/（rv_asm.py、hex2vh.py、run_regress.ps1）、programs/（汇编源码与期望值）。
  仓库根目录的 rtl/、board/、testbench/、tools/ 已删除（删除前逐个文件比对过 MD5，
  与工程目录里的副本完全一致），说明文档仍放在最外层
  cpu21_riscv_redirect_int_bpb说明.md。
- .gitignore 改为：忽略 pipelined-cpu/ 下的工程生成物（*.xpr、*.runs、*.sim、*.cache…），
  只跟踪 srcs/、tools/、programs/、create_project.tcl；_tmp/、_vivado/ 等本地临时目录
  继续忽略。
- 新增 tools/run_regress.ps1：一键回归脚本。编译 srcs/rtl/ → 跑 muldiv/isa/lui/mmio
  四个指令测试并与 programs/*.expected 逐值比对 → 跑两个流水基线 → 跑板级顶层
  （-d BOARD_ROM_FAST）检查跑马灯，最后汇总 PASS/FAIL 并返回失败数作为退出码。
  编译与仿真的中间文件写在 %TEMP%\cpu21_regress，不污染工程目录。实测全部通过。
- 新增 programs/board_demo_fast.asm：快速版演示程序（延时初值 64，约 2.6 µs/步），
  对应 srcs/board/cpu21_board_rom_fast.vh；仿真时用 -d BOARD_ROM_FAST 才会选到它。
- 两个测试平台增加 srcs/rom 探测路径，工程目录内直接 Run Simulation 即可加载镜像。
- 文档：目录结构一节按新布局重写；新增“回归测试”一节（脚本用法 + 期望基线数字）；
  上板章节的生成/仿真命令改为相对工程目录（python tools/rv_asm.py programs/…、
  xvlog -d BOARD_ROM_FAST srcs/rtl/*.v …）；tools 里的用法示例同步更新；
  “工程分享”一节去掉已不存在的副本同步说明。
- 清理：删除本地 _tmp/（约 57 MB）、_vivado/、.Xil/ 临时目录。
This commit is contained in:
Anccend
2026-09-13 19:09:36 +08:00
parent fed01f5910
commit cb0cb433ac
51 changed files with 506 additions and 81 deletions
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pipelined-cpu/tools/hex2vh.py
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#!/usr/bin/env python3
"""把 $readmemh 格式的 hex 文件转换成 Verilog include 文件，供综合时初始化 ROM。
用法: python tools/hex2vh.py <input.hex> <output.vh> [ROM_WORDS]
输出内容形如（每行一条赋值，未用到的地址填 NOP 0x00000013）：
rom[0] = 32'h00001037;
rom[1] = 32'h00100093;
配套 RTL 用法（见 srcs/board/cpu21_board_top.v，两者同目录，所以 include 能直接解析）：
initial begin
for (i = 0; i < ROM_WORDS; i = i + 1) rom[i] = 32'h0000_0013; // NOP 填充
`include "cpu21_board_rom.vh"
end
这样 ROM 内容直接跟着 RTL 走，不依赖综合时的当前工作目录，
避免了 $readmemh 相对路径在 Vivado 综合流程里找不到文件（且只报 warning）的坑。
"""
import sys
NOP = 0x00000013
def main():
src, dst = sys.argv[1], sys.argv[2]
words_total = int(sys.argv[3]) if len(sys.argv) > 3 else 1024
words = []
with open(src, encoding="ascii") as f:
for line in f:
line = line.split("//")[0].strip()
if not line:
continue
words.append(int(line, 16))
if len(words) > words_total:
raise SystemExit(
"程序 %d 个字，超过 ROM 容量 %d 个字" % (len(words), words_total)
)
with open(dst, "w", encoding="utf-8") as f:
f.write(" // generated by tools/hex2vh.py - do not edit by hand\n")
f.write(
" // source: %s (%d words, remaining entries filled with NOP)\n"
% (src, len(words))
)
for addr in range(words_total):
w = words[addr] if addr < len(words) else NOP
f.write(" rom[%d] = 32'h%08X;\n" % (addr, w))
print("已生成 %s（%d 个字，源程序 %d 个字）" % (dst, words_total, len(words)))
main()
pipelined-cpu/tools/run_regress.ps1
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# ============================================================================
# cpu21-riscv 回归脚本（Vivado xsim）
#
# 在工程目录 pipelined-cpu/ 下运行：
# powershell -ExecutionPolicy Bypass -File tools\run_regress.ps1
#
# 做四件事：
# 1) 逐个跑指令测试：muldiv_test / isa_test / lui_test / mmio_test，
# 把测试平台打印的 LED 序列与 programs/<名字>.expected 逐值比对；
# 2) 跑两个流水基线（默认 ROM）：tb_no_intr、tb_cpu21_riscv_redirect_int_bpb，
# 只打印 FINAL 统计行，便于和已知基线核对；
# 3) 跑板级顶层（-d BOARD_ROM_FAST），检查跑马灯 LED 序列；
# 4) 最后汇总 PASS/FAIL 并按失败数设置退出码。
#
# 编译与仿真都放在 $env:TEMP\cpu21_regress 下，不会往工程目录写中间文件。
# 需要 xvlog / xelab / xsim 在 PATH 上（Vivado 安装目录的 bin）。
# ============================================================================
$ErrorActionPreference = 'Stop'
$proj = Split-Path -Parent $PSScriptRoot # tools/ 的上一级就是工程目录
$projF = ($proj -replace '\\', '/') # Verilog 字符串里要用正斜杠
$sim = Join-Path $env:TEMP 'cpu21_regress'
$enc = New-Object System.Text.UTF8Encoding($false)
foreach ($tool in 'xvlog', 'xelab', 'xsim') {
if (-not (Get-Command $tool -ErrorAction SilentlyContinue)) {
Write-Output "ERROR: 找不到 $tool，请把 Vivado 的 bin 目录加到 PATH"
exit 1
}
}
New-Item -ItemType Directory -Force $sim | Out-Null
Set-Content -Path "$sim\run.tcl" -Value @('run all', 'quit') -Encoding ascii
$RTL = @(Get-ChildItem "$proj\srcs\rtl\*.v" | ForEach-Object FullName)
$fail = 0
# TB 里的 ROM_FILE 参数默认是文件名，这里替换成绝对路径（PowerShell 传参有坑，
# 直接改副本最稳）
function Sim-Top {
param($Top, $TbFile, $DefaultRom, $RealRom, $Snap)
$txt = [System.IO.File]::ReadAllText($TbFile, $enc)
$new = $txt.Replace('"' + $DefaultRom + '"', '"' + $projF + '/srcs/rom/' + $RealRom + '"')
[System.IO.File]::WriteAllText("$sim\$Snap.v", $new, $enc)
Remove-Item -Recurse -Force "$sim\xsim.dir" -ErrorAction SilentlyContinue
& xvlog @RTL "$sim\$Snap.v" 2>&1 | Out-File -Encoding ascii "$sim\xvlog_$Snap.txt"
& xelab -top $Top -snapshot $Snap 2>&1 | Out-File -Encoding ascii "$sim\xelab_$Snap.txt"
& xsim $Snap -tclbatch run.tcl 2>&1 | Out-File -Encoding ascii "$sim\run_$Snap.txt"
$err = Select-String -Path "$sim\xvlog_$Snap.txt", "$sim\xelab_$Snap.txt" -Pattern 'ERROR' |
Select-Object -First 1 -ExpandProperty Line
if ($err) { Write-Output "!! $Snap : $err"; $script:fail++ }
}
Push-Location $sim
try {
Write-Output '===== 1) 指令测试（tb_no_intr，与 programs/*.expected 比对）====='
foreach ($t in 'muldiv_test', 'isa_test', 'lui_test', 'mmio_test') {
Sim-Top -Top tb_no_intr -TbFile "$proj\srcs\tb\tb_no_intr.v" `
-DefaultRom 'risc-v-benchmark_ccab.hex' -RealRom "$t.hex" -Snap "sim_$t"
$log = "$sim\run_sim_$t.txt"
$obs = @(Select-String -Path $log -Pattern 'LEDv=1 LED=([0-9a-fA-F]{8})' -AllMatches |
ForEach-Object { $_.Matches[0].Groups[1].Value.ToLower() })
$exp = @(Get-Content "$proj\programs\$t.expected" |
ForEach-Object { $_.Trim().ToLower() } | Where-Object { $_ -ne '' })
if (($obs -join ',') -eq ($exp -join ',')) {
Write-Output (" {0,-13} PASS ({1} 个 LED 值)" -f $t, $obs.Count)
} else {
Write-Output (" {0,-13} FAIL 期望 {1} / 观测 {2}" -f $t, $exp.Count, $obs.Count)
Write-Output (" 期望: " + ($exp -join ' '))
Write-Output (" 观测: " + ($obs -join ' '))
$fail++
}
Write-Output (' ' + (Select-String -Path $log -Pattern 'FINAL:' |
Select-Object -First 1 -ExpandProperty Line))
}
Write-Output '===== 2) 流水基线（默认 ROM）====='
Sim-Top -Top tb_no_intr -TbFile "$proj\srcs\tb\tb_no_intr.v" `
-DefaultRom 'risc-v-benchmark_ccab.hex' -RealRom 'risc-v-benchmark_ccab.hex' -Snap 'base_no_intr'
Write-Output (' tb_no_intr : ' + (Select-String -Path "$sim\run_base_no_intr.txt" -Pattern 'FINAL:' |
Select-Object -First 1 -ExpandProperty Line))
Sim-Top -Top tb_cpu21_riscv_redirect_int_bpb -TbFile "$proj\srcs\tb\tb_cpu21_riscv_redirect_int_bpb.v" `
-DefaultRom 'cpu21_riscv_redirect_int_bpb_rom.hex' -RealRom 'cpu21_riscv_redirect_int_bpb_rom.hex' `
-Snap 'base_intr'
Write-Output (' tb_intr : ' + (Select-String -Path "$sim\run_base_intr.txt" -Pattern 'FINAL:' |
Select-Object -First 1 -ExpandProperty Line))
Write-Output '===== 3) 板级顶层（-d BOARD_ROM_FAST，跑马灯）====='
Remove-Item -Recurse -Force "$sim\xsim.dir" -ErrorAction SilentlyContinue
& xvlog -d BOARD_ROM_FAST @RTL "$proj\srcs\board\cpu21_board_top.v" "$proj\srcs\tb\tb_board_top.v" 2>&1 |
Out-File -Encoding ascii "$sim\xvlog_board.txt"
& xelab -top tb_board_top -snapshot board -d BOARD_ROM_FAST 2>&1 | Out-File -Encoding ascii "$sim\xelab_board.txt"
& xsim board -tclbatch run.tcl 2>&1 | Out-File -Encoding ascii "$sim\run_board.txt"
$seq = @(Select-String -Path "$sim\run_board.txt" -Pattern 'LED=([0-9a-f]{4})' -AllMatches |
ForEach-Object { $_.Matches[0].Groups[1].Value })
Write-Output (' 前 18 个 LED: ' + (($seq[0..17]) -join ' '))
Write-Output (" 变化次数: " + $seq.Count)
if (($seq[0..17] -join ' ') -ne '0000 0001 0002 0004 0008 0010 0020 0040 0080 0100 0200 0400 0800 1000 2000 4000 8000 0001') {
Write-Output ' FAIL：跑马灯序列与预期不符'; $fail++
} else {
Write-Output ' PASS'
}
} finally {
Pop-Location
}
Write-Output ''
if ($fail -eq 0) { Write-Output '全部通过 (所有回归 PASS)' } else { Write-Output "有 $fail 项失败" }
exit $fail
pipelined-cpu/tools/rv_asm.py
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#!/usr/bin/env python3
"""极简 RISC-V 汇编器：仅支持本项目测试所需的指令子集。
用法: python tools/rv_asm.py <input.asm> <output.hex>
同时生成 <output.hex>.lst 反汇编/编码清单，便于核对。
支持：add/sub/and/or/xor/sll/srl/sra/slt/sltu、
mul/mulh/mulhsu/mulhu、
addi/slti/sltiu/xori/ori/andi、slli/srli/srai、
lw/sw/sb、beq/bne/blt/bge/bltu/bgeu、lui、jal/jalr、ecall、标签、# 注释
伪指令：print（= lui t6,LED_ADDR>>12 + sw a0,0(t6)，向 MMIO 的 LED 寄存器写入 a0）、
halt（= addi a7,zero,10 + ecall），各占两个字。
示例：python tools/rv_asm.py programs/isa_test.asm srcs/rom/isa_test.hex
"""
import re
import sys
REGS = {
"zero": 0,
"ra": 1,
"sp": 2,
"gp": 3,
"tp": 4,
"t0": 5,
"t1": 6,
"t2": 7,
"s0": 8,
"s1": 9,
"a0": 10,
"a1": 11,
"a2": 12,
"a3": 13,
"a4": 14,
"a5": 15,
"a6": 16,
"a7": 17,
"s2": 18,
"s3": 19,
"s4": 20,
"s5": 21,
"s6": 22,
"s7": 23,
"s8": 24,
"s9": 25,
"s10": 26,
"s11": 27,
"t3": 28,
"t4": 29,
"t5": 30,
"t6": 31,
}
def reg(t):
t = t.strip()
if t in REGS:
return REGS[t]
m = re.fullmatch(r"x(\d+)", t)
if m:
return int(m.group(1))
raise SystemExit("未知寄存器: " + t)
def num(t):
return int(t.strip(), 0)
def enc_r(f7, rs2, rs1, f3, rd):
return (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33
def enc_i(imm, rs1, f3, rd, op=0x13):
return ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | op
def enc_s(imm, rs2, rs1, f3):
imm &= 0xFFF
return (
((imm >> 5) << 25)
| (rs2 << 20)
| (rs1 << 15)
| (f3 << 12)
| ((imm & 0x1F) << 7)
| 0x23
)
def enc_b(imm, rs2, rs1, f3):
imm &= 0x1FFF
return (
(((imm >> 12) & 1) << 31)
| (((imm >> 5) & 0x3F) << 25)
| (rs2 << 20)
| (rs1 << 15)
| (f3 << 12)
| (((imm >> 1) & 0xF) << 8)
| (((imm >> 11) & 1) << 7)
| 0x63
)
def enc_u(imm, rd):
return ((imm & 0xFFFFF) << 12) | (rd << 7) | 0x37
def enc_j(imm, rd):
imm &= 0x1FFFFF
return (
(((imm >> 20) & 1) << 31)
| (((imm >> 1) & 0x3FF) << 21)
| (((imm >> 11) & 1) << 20)
| (((imm >> 12) & 0xFF) << 12)
| (rd << 7)
| 0x6F
)
RTYPE = {
"add": (0x00, 0),
"sub": (0x20, 0),
"sll": (0x00, 1),
"slt": (0x00, 2),
"sltu": (0x00, 3),
"xor": (0x00, 4),
"srl": (0x00, 5),
"sra": (0x20, 5),
"or": (0x00, 6),
"and": (0x00, 7),
"mul": (0x01, 0),
"mulh": (0x01, 1),
"mulhsu": (0x01, 2),
"mulhu": (0x01, 3),
"divu": (0x01, 5),
"remu": (0x01, 7),
}
ITYPE = {"addi": 0, "slti": 2, "sltiu": 3, "xori": 4, "ori": 6, "andi": 7}
SHIFT = {"slli": 1, "srli": 5, "srai": 5}
BTYPE = {"beq": 0, "bne": 1, "blt": 4, "bge": 5, "bltu": 6, "bgeu": 7}
# MMIO：LED 数据寄存器地址，需与 RTL 顶层 parameter LED_ADDR 保持一致
LED_ADDR = 0x1000
# 双字伪指令：print 向 MMIO 的 LED 写寄存器写入 a0；halt 停机
PSEUDO_SIZE = {"print": 2, "halt": 2}
def assemble(lines):
labels, items, addr = {}, [], 0
for raw in lines:
line = raw.split("#")[0].strip()
if not line:
continue
while True:
m = re.match(r"^([A-Za-z_.$][\w.$]*)\s*:\s*(.*)$", line)
if not m:
break
labels[m.group(1)] = addr
line = m.group(2).strip()
if not line:
break
if not line:
continue
items.append((addr, line))
addr += 4 * PSEUDO_SIZE.get(line.split()[0].lower(), 1)
out = []
for addr, line in items:
parts = re.split(r"[\s,]+", line)
mn, a = parts[0].lower(), parts[1:]
if mn in RTYPE:
f7, f3 = RTYPE[mn]
w = enc_r(f7, reg(a[2]), reg(a[1]), f3, reg(a[0]))
elif mn in ITYPE:
im = num(a[2])
if not (-2048 <= im <= 2047):
raise SystemExit("I 型立即数超出 12 位有符号范围: " + line)
w = enc_i(im, reg(a[1]), ITYPE[mn], reg(a[0]))
elif mn in SHIFT:
w = enc_i(num(a[2]) & 0x1F, reg(a[1]), SHIFT[mn], reg(a[0]))
elif mn == "lui":
w = enc_u(num(a[1]), reg(a[0]))
elif mn in ("lw", "sw", "sb"):
m = re.fullmatch(r"(-?\w+)\((\w+)\)", a[1])
if not m:
raise SystemExit("内存操作数格式应为 imm(rs1): " + line)
im = num(m.group(1))
if not (-2048 <= im <= 2047):
raise SystemExit("访存偏移超出 12 位有符号范围: " + line)
if mn == "lw":
w = enc_i(im, reg(m.group(2)), 2, reg(a[0]), 0x03)
elif mn == "sw":
w = enc_s(im, reg(a[0]), reg(m.group(2)), 2)
else: # sb
w = enc_s(im, reg(a[0]), reg(m.group(2)), 0)
elif mn in BTYPE:
tgt = labels[a[2]] if a[2] in labels else num(a[2])
w = enc_b(tgt - addr, reg(a[1]), reg(a[0]), BTYPE[mn])
elif mn == "jal":
tgt = labels[a[1]] if a[1] in labels else num(a[1])
w = enc_j(tgt - addr, reg(a[0]))
elif mn == "jalr":
w = enc_i(num(a[2]), reg(a[1]), 0, reg(a[0]), 0x67)
elif mn == "ecall":
w = 0x00000073
elif mn == "print":
# 写 MMIO 的 LED 寄存器：lui t6, LED_ADDR>>12 ; sw a0, 0(t6)
w = [
enc_u(LED_ADDR >> 12, reg("t6")),
enc_s(0, reg("a0"), reg("t6"), 2),
]
elif mn == "halt":
w = [enc_i(10, 0, 0, 17), 0x00000073]
else:
raise SystemExit("未知助记符: " + mn)
out.append((addr, line, w if isinstance(w, list) else [w]))
return out
def main():
src, dst = sys.argv[1], sys.argv[2]
with open(src, encoding="utf-8-sig") as f: # 兼容带/不带 BOM
prog = assemble(f.readlines())
with open(dst, "w", encoding="ascii") as f:
for _, _, ws in prog:
for w in ws:
f.write("%08X\n" % w)
with open(dst + ".lst", "w", encoding="utf-8") as f:
for addr, line, ws in prog:
f.write("%04X: %s %s\n" % (addr, " ".join("%08X" % w for w in ws), line))
print("已生成 %s（%d 个字）" % (dst, sum(len(ws) for _, _, ws in prog)))
main()