源文件收敛到 pipelined-cpu/ 一份：删除根目录 rtl/board/testbench/tools，补充回归脚本
- 现在只有一份源文件，就在 pipelined-cpu/ 下：
srcs/rtl（13 个处理器 RTL）、srcs/board、srcs/constrs、srcs/tb、srcs/rom、
tools/（rv_asm.py、hex2vh.py、run_regress.ps1）、programs/（汇编源码与期望值）。
仓库根目录的 rtl/、board/、testbench/、tools/ 已删除（删除前逐个文件比对过 MD5，
与工程目录里的副本完全一致），说明文档仍放在最外层
cpu21_riscv_redirect_int_bpb说明.md。
- .gitignore 改为：忽略 pipelined-cpu/ 下的工程生成物（*.xpr、*.runs、*.sim、*.cache…），
只跟踪 srcs/、tools/、programs/、create_project.tcl；_tmp/、_vivado/ 等本地临时目录
继续忽略。
- 新增 tools/run_regress.ps1：一键回归脚本。编译 srcs/rtl/ → 跑 muldiv/isa/lui/mmio
四个指令测试并与 programs/*.expected 逐值比对 → 跑两个流水基线 → 跑板级顶层
（-d BOARD_ROM_FAST）检查跑马灯，最后汇总 PASS/FAIL 并返回失败数作为退出码。
编译与仿真的中间文件写在 %TEMP%\cpu21_regress，不污染工程目录。实测全部通过。
- 新增 programs/board_demo_fast.asm：快速版演示程序（延时初值 64，约 2.6 µs/步），
对应 srcs/board/cpu21_board_rom_fast.vh；仿真时用 -d BOARD_ROM_FAST 才会选到它。
- 两个测试平台增加 srcs/rom 探测路径，工程目录内直接 Run Simulation 即可加载镜像。
- 文档：目录结构一节按新布局重写；新增“回归测试”一节（脚本用法 + 期望基线数字）；
上板章节的生成/仿真命令改为相对工程目录（python tools/rv_asm.py programs/…、
xvlog -d BOARD_ROM_FAST srcs/rtl/*.v …）；tools 里的用法示例同步更新；
“工程分享”一节去掉已不存在的副本同步说明。
- 清理：删除本地 _tmp/（约 57 MB）、_vivado/、.Xil/ 临时目录。
This commit is contained in:
@@ -0,0 +1,117 @@
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`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// 八表项全相联分支目标缓冲（BPB/BTB）。
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//
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// tag = PC[11:2]，与 Logisim 版 BPB 中的十位 tag 拆分保持一致。
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// count 为两位饱和计数器：00/01 表示不跳转，10/11 表示跳转。
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// age 用于近似 LRU 替换：被选中的表项清零，其余表项自增。
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// -----------------------------------------------------------------------------
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module cpu21_bpb_8 (
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input wire clk,
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input wire reset,
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input wire [31:0] predict_pc,
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input wire predict_enable,
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output reg predict_hit,
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output reg predict_taken,
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output reg [31:0] predict_target,
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input wire update_enable,
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input wire update_controlflow,
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input wire [31:0] update_pc,
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input wire [31:0] update_target,
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input wire update_taken
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);
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reg valid [0:7];
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reg [ 9:0] tag [0:7];
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reg [31:0] target [0:7];
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reg [ 1:0] count [0:7];
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reg [ 2:0] age [0:7];
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reg update_found;
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reg [ 2:0] update_index;
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reg replace_found;
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reg [ 2:0] replace_index;
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reg [ 2:0] max_age;
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integer p;
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integer u;
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integer k;
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integer selected_index;
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// 预测命中查找：按 tag 全相联匹配，命中则给出目标地址与方向预测。
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always @* begin
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predict_hit = 1'b0;
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predict_taken = 1'b0;
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predict_target = 32'b0;
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for (p = 0; p < 8; p = p + 1) begin
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if (predict_enable && !predict_hit && valid[p] && (tag[p] == predict_pc[11:2])) begin
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predict_hit = 1'b1;
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predict_target = target[p];
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predict_taken = count[p][1];
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end
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end
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end
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// 更新时先找匹配表项；若无匹配则优先使用无效表项，否则淘汰最旧表项。
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// 下方的 age 自增实现了类似 LRU 的替换策略。
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always @* begin
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update_found = 1'b0;
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update_index = 3'd0;
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replace_found = 1'b0;
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replace_index = 3'd0;
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max_age = 3'd0;
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for (u = 0; u < 8; u = u + 1) begin
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if (!update_found && valid[u] && (tag[u] == update_pc[11:2])) begin
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update_found = 1'b1;
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update_index = u;
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end
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end
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for (u = 0; u < 8; u = u + 1) begin
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if (!replace_found && !valid[u]) begin
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replace_found = 1'b1;
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replace_index = u;
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end else if (!replace_found && (age[u] >= max_age)) begin
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replace_index = u;
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max_age = age[u];
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end
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end
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end
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// 表项状态更新（含替换与两位饱和计数器更新）。
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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for (k = 0; k < 8; k = k + 1) begin
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valid[k] <= 1'b0;
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tag[k] <= 10'b0;
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target[k] <= 32'b0;
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count[k] <= 2'b01;
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age[k] <= 3'b0;
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end
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end else if (update_enable && update_controlflow) begin
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selected_index = update_found ? update_index : replace_index;
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valid[selected_index] <= 1'b1;
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tag[selected_index] <= update_pc[11:2];
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target[selected_index] <= update_target;
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age[selected_index] <= 3'b0;
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if (!update_found) begin
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// 新表项采用较弱的初始状态，避免立刻产生错误预测。
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count[selected_index] <= update_taken ? 2'b10 : 2'b01;
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end else if (update_taken) begin
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// 实际跳转：计数器加一（饱和到 11）。
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if (count[selected_index] != 2'b11) count[selected_index] <= count[selected_index] + 2'b01;
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end else begin
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// 实际不跳转：计数器减一（饱和到 00）。
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if (count[selected_index] != 2'b00) count[selected_index] <= count[selected_index] - 2'b01;
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end
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for (k = 0; k < 8; k = k + 1) begin
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if (valid[k] && (k != selected_index) && (age[k] != 3'b111)) age[k] <= age[k] + 3'b001;
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end
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end
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end
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endmodule
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`default_nettype wire
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@@ -0,0 +1,62 @@
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`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// MMIO：把外设寄存器映射到数据存储器地址空间。
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//
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// 目前实现 LED 数据寄存器（LED_ADDR 默认 0x0000_1000，位于 4 KB 数据 RAM 之外）：
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// * 写：sw / sb 命中该地址（按字对齐，即同一 32 位寄存器内的任意字节偏移
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// 都算命中）时更新 LED 寄存器，led_valid_o 拉高一拍；sb 依据 wstrb_i 只
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// 修改对应的字节通道（与 RAM 的字节写语义一致）。
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// * 读：lw 命中该地址时 rdata_hit_o 拉高，顶层据此选择本模块的 rdata_o
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// 而不是外部 data_rdata_i，从而支持把 LED 值读回。
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//
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// 以后要增加外设（拨码开关、UART 等）时只需在这里扩展地址译码，
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// 处理器核心与流水线时序不需要改动。
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// -----------------------------------------------------------------------------
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module cpu21_mmio #(
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parameter [31:0] LED_ADDR = 32'h0000_1000
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) (
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input wire clk,
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input wire reset,
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// MEM 级的访存请求（来自 EX/MEM 流水寄存器）
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input wire mem_valid_i,
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input wire mem_write_i,
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input wire mem_read_i,
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input wire [31:0] addr_i,
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input wire [31:0] wdata_i,
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input wire [ 3:0] wstrb_i,
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// MMIO 读回
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output wire [31:0] rdata_o,
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output wire rdata_hit_o,
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// LED 外设
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output reg [31:0] led_data_o,
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output reg led_valid_o
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);
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// 地址译码按“字”对齐：同一 32 位寄存器内的任意字节偏移都算命中，
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// 具体修改哪几个字节由 wstrb_i 决定（sw 全字、sb 单字节）。
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wire led_wr = mem_valid_i && mem_write_i && (addr_i[31:2] == LED_ADDR[31:2]);
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wire led_rd = mem_valid_i && mem_read_i && (addr_i[31:2] == LED_ADDR[31:2]);
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assign rdata_hit_o = led_rd;
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assign rdata_o = led_data_o;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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led_data_o <= 32'b0;
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led_valid_o <= 1'b0;
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end else begin
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// led_valid_o 只拉高一拍，作为“本周期有 LED 写入”的指示。
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led_valid_o <= 1'b0;
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if (led_wr) begin
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if (wstrb_i[0]) led_data_o[7:0] <= wdata_i[7:0];
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if (wstrb_i[1]) led_data_o[15:8] <= wdata_i[15:8];
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if (wstrb_i[2]) led_data_o[23:16] <= wdata_i[23:16];
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if (wstrb_i[3]) led_data_o[31:24] <= wdata_i[31:24];
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led_valid_o <= 1'b1;
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end
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end
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end
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endmodule
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`default_nettype wire
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@@ -0,0 +1,65 @@
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`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// ALU：组合运算单元（只做加减/移位/逻辑/比较等单拍运算）。
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//
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// 乘法与除法已移到 cpu21_riscv_muldiv.v（时序多周期单元），因为组合的 a*b / a%b
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// 关键路径过长（综合后约 94 ns，100 MHz 下无法收敛）。因此本模块不再实现
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// ALU_MUL / ALU_DIVU：这两个操作码只作为“这是乘除法指令”的标识，对应结果由
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// 顶层从 muldiv 的输出选取（result2 的 wb_sel=3 约定保持不变）。
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//
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// result 为主结果；result2 为第二结果，由译码器用 wb_sel=3 选取。
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// -----------------------------------------------------------------------------
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module cpu21_riscv_alu (
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input wire [ 3:0] op,
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input wire [31:0] a,
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input wire [31:0] b,
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output reg [31:0] result,
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output reg [31:0] result2
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);
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localparam ALU_SLL = 4'd0;
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localparam ALU_SRA = 4'd1;
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localparam ALU_SRL = 4'd2;
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localparam ALU_MUL = 4'd3;
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localparam ALU_DIVU = 4'd4;
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localparam ALU_ADD = 4'd5;
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localparam ALU_SUB = 4'd6;
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localparam ALU_AND = 4'd7;
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localparam ALU_OR = 4'd8;
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localparam ALU_XOR = 4'd9;
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localparam ALU_NOR = 4'd10;
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localparam ALU_SLT = 4'd11;
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localparam ALU_SLTU = 4'd12;
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localparam ALU_MULH = 4'd13;
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localparam ALU_MULHSU = 4'd14;
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localparam ALU_PASSB = 4'd15; // 直接输出 B 端（供 LUI 使用）
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always @* begin
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result = 32'b0;
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result2 = 32'b0;
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case (op)
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ALU_SLL: result = a << b[4:0];
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ALU_SRA: result = $signed(a) >>> b[4:0];
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ALU_SRL: result = a >> b[4:0];
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// 乘法（ALU_MUL）与除法（ALU_DIVU）在本模块内不产生结果：
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// 它们由 cpu21_riscv_muldiv 多周期单元完成，顶层用 ex_muldiv 选择其输出。
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ALU_MUL: ;
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ALU_DIVU: ;
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ALU_ADD: result = a + b;
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ALU_SUB: result = a - b;
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ALU_AND: result = a & b;
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ALU_OR: result = a | b;
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ALU_XOR: result = a ^ b;
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ALU_NOR: result = ~(a | b);
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ALU_SLT: result = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;
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ALU_SLTU: result = (a < b) ? 32'd1 : 32'd0;
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ALU_MULH: ;
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ALU_MULHSU: ;
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ALU_PASSB: result = b;
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default: result = 32'b0;
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endcase
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end
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endmodule
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`default_nettype wire
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@@ -0,0 +1,68 @@
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`timescale 1ns / 1ps
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`default_nettype none
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// -----------------------------------------------------------------------------
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// EX 级控制流裁决单元。
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//
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// 条件分支的实际方向与目标都在 EX 级解析；JAL/JALR 的目标也只在 EX 级
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// 得到，因此它们总是需要重定向。条件分支仅在预测方向/目标与实际不符时
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// 才重定向，这样预测正确时不会产生气泡。
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// -----------------------------------------------------------------------------
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module cpu21_riscv_branch_unit (
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input wire valid_i,
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input wire [31:0] pc_i,
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input wire [31:0] imm_i,
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input wire [31:0] src1_i,
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input wire [31:0] src2_i,
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input wire branch_i,
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input wire beq_i,
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input wire bne_i,
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input wire blt_i,
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input wire bge_i,
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input wire bltu_i,
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input wire bgeu_i,
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input wire jal_i,
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input wire jalr_i,
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// IF 级携带过来的预测信息
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input wire pred_taken_i,
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input wire [31:0] pred_target_i,
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// 裁决结果
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output wire branch_taken_o,
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output wire controlflow_o,
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output wire [31:0] target_o,
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output wire redirect_valid_o,
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output wire [31:0] redirect_pc_o
|
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);
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// 比较结果预先算好，避免表达式过长被自动换行拆散。
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wire lt_signed = $signed(src1_i) < $signed(src2_i);
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wire ge_signed = $signed(src1_i) >= $signed(src2_i);
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wire lt_unsigned = src1_i < src2_i;
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wire ge_unsigned = src1_i >= src2_i;
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// 条件分支裁决：beq 相等、bne 不等、blt/bge 有符号比较、bltu/bgeu 无符号比较。
|
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assign branch_taken_o = branch_i &&
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((beq_i && (src1_i == src2_i)) ||
|
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(bne_i && (src1_i != src2_i)) ||
|
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(blt_i && lt_signed) ||
|
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(bge_i && ge_signed) ||
|
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(bltu_i && lt_unsigned) ||
|
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(bgeu_i && ge_unsigned));
|
||||
|
||||
// 跳转目标：jalr 为 (rs1+imm) 且最低位清零；jal 为 PC+imm。
|
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assign target_o = jalr_i ? ((src1_i + imm_i) & 32'hffff_fffe) : (pc_i + imm_i);
|
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|
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// EX 级存在需要裁决的控制流指令。
|
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assign controlflow_o = valid_i && (branch_i || jal_i || jalr_i);
|
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|
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// 条件分支的预测方向/目标与实际不符，或 JAL/JALR 必须重定向。
|
||||
assign redirect_valid_o = controlflow_o &&
|
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(branch_i ?
|
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((pred_taken_i != branch_taken_o) ||
|
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(pred_taken_i && branch_taken_o &&
|
||||
(pred_target_i != target_o))) : 1'b1);
|
||||
|
||||
// 预测了跳转但实际不跳转时，回到顺序地址继续取指。
|
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assign redirect_pc_o = (branch_i && !branch_taken_o) ? (pc_i + 32'd4) : target_o;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,309 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// ID 级组合译码器。
|
||||
//
|
||||
// 与原始 Logisim 控制器一致：操作码取标准 RISC-V 的 IR[6:2] 五位字段，
|
||||
// 真值表中以十六进制形式存储该字段。
|
||||
// 所有输出在无匹配时保持"无操作/不写回"的默认值。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_decoder (
|
||||
input wire [31:0] ir_i,
|
||||
|
||||
output reg [ 4:0] rs1_idx_o,
|
||||
output reg [ 4:0] rs2_idx_o,
|
||||
output reg [ 4:0] rd_o,
|
||||
output reg [31:0] imm_o,
|
||||
output reg [ 3:0] alu_op_o,
|
||||
output reg [ 2:0] wb_sel_o,
|
||||
output reg [ 2:0] md_op_o,
|
||||
output wire [11:0] csr_addr_o,
|
||||
output reg uses_rs1_o,
|
||||
output reg uses_rs2_o,
|
||||
output reg reg_write_o,
|
||||
output reg mem_to_reg_o,
|
||||
output reg mem_write_o,
|
||||
output reg mem_byte_o,
|
||||
output reg alu_src_o,
|
||||
output reg branch_o,
|
||||
output reg beq_o,
|
||||
output reg bne_o,
|
||||
output reg blt_o,
|
||||
output reg bge_o,
|
||||
output reg bltu_o,
|
||||
output reg bgeu_o,
|
||||
output reg jal_o,
|
||||
output reg jalr_o,
|
||||
output reg ecall_o,
|
||||
output reg uret_o,
|
||||
output reg csr_set_o,
|
||||
output reg csr_clear_o,
|
||||
output reg csr_write_o
|
||||
);
|
||||
// CPU21 自定义操作码（取自所提供的真值表）。
|
||||
localparam OP_LOAD = 5'h00;
|
||||
localparam OP_R = 5'h0c;
|
||||
localparam OP_I = 5'h04;
|
||||
localparam OP_STORE = 5'h08;
|
||||
localparam OP_JALR = 5'h19;
|
||||
localparam OP_BRANCH = 5'h18;
|
||||
localparam OP_JAL = 5'h1b;
|
||||
localparam OP_SYS = 5'h1c;
|
||||
// LUI 为扩展指令（标准 RISC-V opcode 0x37 -> IR[6:2]=0x0d）。
|
||||
localparam OP_LUI = 5'h0d;
|
||||
|
||||
localparam ALU_SLL = 4'd0;
|
||||
localparam ALU_SRA = 4'd1;
|
||||
localparam ALU_SRL = 4'd2;
|
||||
localparam ALU_MUL = 4'd3;
|
||||
localparam ALU_DIVU = 4'd4;
|
||||
localparam ALU_ADD = 4'd5;
|
||||
localparam ALU_SUB = 4'd6;
|
||||
localparam ALU_AND = 4'd7;
|
||||
localparam ALU_OR = 4'd8;
|
||||
localparam ALU_XOR = 4'd9;
|
||||
localparam ALU_SLT = 4'd11;
|
||||
localparam ALU_SLTU = 4'd12;
|
||||
localparam ALU_MULH = 4'd13;
|
||||
localparam ALU_MULHSU = 4'd14;
|
||||
localparam ALU_PASSB = 4'd15; // LUI：直接输出 B 端（立即数）
|
||||
|
||||
// 乘除法单元（cpu21_riscv_muldiv）的操作编码，MD_NONE 表示非乘除法指令。
|
||||
localparam [2:0] MD_NONE = 3'd0;
|
||||
localparam [2:0] MD_MUL = 3'd1;
|
||||
localparam [2:0] MD_MULH = 3'd2;
|
||||
localparam [2:0] MD_MULHSU = 3'd3;
|
||||
localparam [2:0] MD_MULHU = 3'd4;
|
||||
localparam [2:0] MD_DIVU = 3'd5;
|
||||
localparam [2:0] MD_REMU = 3'd6;
|
||||
|
||||
wire [4:0] opcode = ir_i[6:2];
|
||||
wire [2:0] funct3 = ir_i[14:12];
|
||||
wire [6:0] funct7 = ir_i[31:25];
|
||||
|
||||
// CSR 地址字段在译码时直接旁路输出（供 EX 级读取 CSR）。
|
||||
assign csr_addr_o = ir_i[31:20];
|
||||
|
||||
// 默认控制信号：全部为"无操作/不写回"，再由下面的 case 覆盖。
|
||||
always @* begin
|
||||
rs1_idx_o = ir_i[19:15];
|
||||
rs2_idx_o = ir_i[24:20];
|
||||
rd_o = ir_i[11:7];
|
||||
imm_o = {{20{ir_i[31]}}, ir_i[31:20]};
|
||||
alu_op_o = ALU_ADD;
|
||||
wb_sel_o = 3'd0;
|
||||
md_op_o = MD_NONE;
|
||||
uses_rs1_o = 1'b0;
|
||||
uses_rs2_o = 1'b0;
|
||||
reg_write_o = 1'b0;
|
||||
mem_to_reg_o = 1'b0;
|
||||
mem_write_o = 1'b0;
|
||||
mem_byte_o = 1'b0;
|
||||
alu_src_o = 1'b0;
|
||||
branch_o = 1'b0;
|
||||
beq_o = 1'b0;
|
||||
bne_o = 1'b0;
|
||||
blt_o = 1'b0;
|
||||
bge_o = 1'b0;
|
||||
bltu_o = 1'b0;
|
||||
bgeu_o = 1'b0;
|
||||
jal_o = 1'b0;
|
||||
jalr_o = 1'b0;
|
||||
ecall_o = 1'b0;
|
||||
uret_o = 1'b0;
|
||||
csr_set_o = 1'b0;
|
||||
csr_clear_o = 1'b0;
|
||||
csr_write_o = 1'b0;
|
||||
|
||||
case (opcode)
|
||||
// R 型运算：由 funct3/funct7 决定具体操作。
|
||||
OP_R: begin
|
||||
uses_rs1_o = 1'b1;
|
||||
uses_rs2_o = 1'b1;
|
||||
reg_write_o = 1'b1;
|
||||
// M 扩展（funct7=0000001）：mul/mulh/mulhsu/mulhu，以及课程真值表里的
|
||||
// divu（funct3=101，商）与 remu（funct3=111，余数）。它们都由多周期
|
||||
// 乘除法单元完成，这里只给出操作类型 md_op_o；mulhu 与 remu 依旧用
|
||||
// wb_sel=3 取 result2（高位乘积 / 余数）。
|
||||
if (funct7 == 7'b0000001) begin
|
||||
case (funct3)
|
||||
3'b000: begin // mul：低 32 位
|
||||
alu_op_o = ALU_MUL;
|
||||
md_op_o = MD_MUL;
|
||||
end
|
||||
3'b001: begin // mulh：有符号高 32 位
|
||||
alu_op_o = ALU_MULH;
|
||||
md_op_o = MD_MULH;
|
||||
end
|
||||
3'b010: begin // mulhsu：有符号 x 无符号高 32 位
|
||||
alu_op_o = ALU_MULHSU;
|
||||
md_op_o = MD_MULHSU;
|
||||
end
|
||||
3'b011: begin // mulhu：无符号高 32 位
|
||||
alu_op_o = ALU_MUL;
|
||||
md_op_o = MD_MULHU;
|
||||
wb_sel_o = 3'd3;
|
||||
end
|
||||
3'b101: begin // divu：无符号商
|
||||
alu_op_o = ALU_DIVU;
|
||||
md_op_o = MD_DIVU;
|
||||
end
|
||||
3'b111: begin // remu：无符号余数
|
||||
alu_op_o = ALU_DIVU;
|
||||
md_op_o = MD_REMU;
|
||||
wb_sel_o = 3'd3;
|
||||
end
|
||||
default: reg_write_o = 1'b0;
|
||||
endcase
|
||||
end else begin
|
||||
// 标准 R 型 funct3 译码；add/sub 与 sra/srl 由 funct7[5] 区分。
|
||||
case (funct3)
|
||||
3'b000: alu_op_o = (funct7[5] ? ALU_SUB : ALU_ADD);
|
||||
3'b001: alu_op_o = ALU_SLL;
|
||||
3'b010: alu_op_o = ALU_SLT;
|
||||
3'b011: alu_op_o = ALU_SLTU;
|
||||
3'b100: alu_op_o = ALU_XOR;
|
||||
3'b101: alu_op_o = (funct7[5] ? ALU_SRA : ALU_SRL);
|
||||
3'b110: alu_op_o = ALU_OR;
|
||||
3'b111: alu_op_o = ALU_AND;
|
||||
default: reg_write_o = 1'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// I 型运算（addi/slli/slti/sltiu/xori/srai/srli/ori/andi）。
|
||||
OP_I: begin
|
||||
uses_rs1_o = 1'b1;
|
||||
alu_src_o = 1'b1;
|
||||
reg_write_o = 1'b1;
|
||||
case (funct3)
|
||||
3'b000: alu_op_o = ALU_ADD; // addi：立即数加
|
||||
3'b001: alu_op_o = ALU_SLL; // slli：立即数逻辑左移
|
||||
3'b010: alu_op_o = ALU_SLT; // slti：有符号小于置 1
|
||||
3'b011: alu_op_o = ALU_SLTU; // sltiu：无符号小于置 1（立即数符号扩展）
|
||||
3'b100: alu_op_o = ALU_XOR; // xori：立即数异或
|
||||
3'b101:
|
||||
alu_op_o = (funct7[5] ? ALU_SRA : ALU_SRL); // srai/srli：立即数算术/逻辑右移
|
||||
3'b110: alu_op_o = ALU_OR; // ori：立即数或
|
||||
3'b111: alu_op_o = ALU_AND; // andi：立即数与
|
||||
default: reg_write_o = 1'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// 加载高位立即数 lui：rd = imm[31:12] << 12。
|
||||
// 不读寄存器；用 ALU_SRC 选立即数，ALU 直通 B 端输出。
|
||||
OP_LUI: begin
|
||||
reg_write_o = 1'b1;
|
||||
alu_src_o = 1'b1;
|
||||
alu_op_o = ALU_PASSB;
|
||||
imm_o = {ir_i[31:12], 12'b0};
|
||||
wb_sel_o = 3'd0;
|
||||
end
|
||||
|
||||
// 加载指令，当前仅支持 lw（funct3=010）。
|
||||
OP_LOAD: begin
|
||||
if (funct3 == 3'b010) begin
|
||||
uses_rs1_o = 1'b1;
|
||||
alu_src_o = 1'b1;
|
||||
alu_op_o = ALU_ADD;
|
||||
mem_to_reg_o = 1'b1;
|
||||
reg_write_o = 1'b1;
|
||||
wb_sel_o = 3'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// 存储指令：sw（funct3=010）与 sb（funct3=000）。
|
||||
OP_STORE: begin
|
||||
if ((funct3 == 3'b010) || (funct3 == 3'b000)) begin
|
||||
uses_rs1_o = 1'b1;
|
||||
uses_rs2_o = 1'b1;
|
||||
alu_src_o = 1'b1;
|
||||
alu_op_o = ALU_ADD;
|
||||
mem_write_o = 1'b1;
|
||||
mem_byte_o = (funct3 == 3'b000); // sb：字节存储
|
||||
imm_o = {{20{ir_i[31]}}, ir_i[31:25], ir_i[11:7]};
|
||||
end
|
||||
end
|
||||
|
||||
// 条件分支：beq（000）/bne（001）/blt（100）/bge（101）/bltu（110）/bgeu（111）。
|
||||
OP_BRANCH: begin
|
||||
if ((funct3 == 3'b000) || (funct3 == 3'b001) || (funct3 == 3'b100) ||
|
||||
(funct3 == 3'b101) || (funct3 == 3'b110) || (funct3 == 3'b111)) begin
|
||||
uses_rs1_o = 1'b1;
|
||||
uses_rs2_o = 1'b1;
|
||||
branch_o = 1'b1;
|
||||
beq_o = (funct3 == 3'b000);
|
||||
bne_o = (funct3 == 3'b001);
|
||||
blt_o = (funct3 == 3'b100);
|
||||
bge_o = (funct3 == 3'b101);
|
||||
bltu_o = (funct3 == 3'b110);
|
||||
bgeu_o = (funct3 == 3'b111);
|
||||
// 有符号比较用 ALU_SLT、无符号比较用 ALU_SLTU，相等/不等用减法；
|
||||
// 分支是否成立由 EX 级的分支裁决单元决定，这里只与真值表保持一致。
|
||||
alu_op_o = (blt_o || bge_o) ? ALU_SLT : ((bltu_o || bgeu_o) ? ALU_SLTU : ALU_SUB);
|
||||
imm_o = {{19{ir_i[31]}}, ir_i[31], ir_i[7], ir_i[30:25], ir_i[11:8], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
// 无条件跳转并链接：jal（写回 PC+4）。
|
||||
OP_JAL: begin
|
||||
jal_o = 1'b1;
|
||||
reg_write_o = 1'b1;
|
||||
wb_sel_o = 3'd2;
|
||||
imm_o = {{11{ir_i[31]}}, ir_i[31], ir_i[19:12], ir_i[20], ir_i[30:21], 1'b0};
|
||||
end
|
||||
|
||||
// 寄存器间接跳转并链接：jalr。
|
||||
OP_JALR: begin
|
||||
if (funct3 == 3'b000) begin
|
||||
jalr_o = 1'b1;
|
||||
uses_rs1_o = 1'b1;
|
||||
alu_src_o = 1'b1;
|
||||
alu_op_o = ALU_ADD;
|
||||
reg_write_o = 1'b1;
|
||||
wb_sel_o = 3'd2;
|
||||
end
|
||||
end
|
||||
|
||||
// 系统指令：ecall / uret / CSR 读写。
|
||||
OP_SYS: begin
|
||||
// 电路用 IR[21] 区分 URET 与 ecall。
|
||||
if (funct3 == 3'b000) begin
|
||||
if (ir_i[21]) begin
|
||||
uret_o = 1'b1;
|
||||
end else begin
|
||||
ecall_o = 1'b1;
|
||||
// 按文档说明，ecall 读取 a7(rs17) 与 a0(rs10)。
|
||||
uses_rs1_o = 1'b1;
|
||||
uses_rs2_o = 1'b1;
|
||||
rs1_idx_o = 5'd17;
|
||||
rs2_idx_o = 5'd10;
|
||||
end
|
||||
end else if (funct3 == 3'b001) begin
|
||||
csr_write_o = 1'b1; // CSRRW：写 CSR，并把旧值写回 rd
|
||||
uses_rs1_o = 1'b1;
|
||||
alu_src_o = 1'b1;
|
||||
imm_o = {27'b0, ir_i[19:15]};
|
||||
reg_write_o = (rd_o != 5'd0);
|
||||
wb_sel_o = 3'd4;
|
||||
end else if (funct3 == 3'b110) begin
|
||||
csr_set_o = 1'b1; // CSRRSI：置位 CSR 中的指定位
|
||||
imm_o = {27'b0, ir_i[19:15]};
|
||||
reg_write_o = (rd_o != 5'd0);
|
||||
wb_sel_o = 3'd4;
|
||||
end else if (funct3 == 3'b111) begin
|
||||
csr_clear_o = 1'b1; // CSRRCI：清除 CSR 中的指定位
|
||||
imm_o = {27'b0, ir_i[19:15]};
|
||||
reg_write_o = (rd_o != 5'd0);
|
||||
wb_sel_o = 3'd4;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,47 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// EX 级前递单元。
|
||||
//
|
||||
// 优先级：EX/MEM 级的结果最新 -> 其次 MEM/WB 级写回值 -> 最后是 ID 级
|
||||
// 译码时读到的寄存器值。load 结果在 MEM 级之后才可用，因此 EX/MEM 的
|
||||
// load（mem_to_reg）不参与前递，改由冒险单元插入一个气泡。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_forward_unit (
|
||||
input wire [31:0] rs1_value_i,
|
||||
input wire [31:0] rs2_value_i,
|
||||
input wire [ 4:0] rs1_idx_i,
|
||||
input wire [ 4:0] rs2_idx_i,
|
||||
// EX/MEM 级
|
||||
input wire exmem_valid_i,
|
||||
input wire exmem_reg_write_i,
|
||||
input wire exmem_mem_to_reg_i,
|
||||
input wire [ 4:0] exmem_rd_i,
|
||||
input wire [31:0] exmem_value_i,
|
||||
// MEM/WB 级
|
||||
input wire memwb_valid_i,
|
||||
input wire memwb_reg_write_i,
|
||||
input wire [ 4:0] memwb_rd_i,
|
||||
input wire [31:0] memwb_value_i,
|
||||
// 前递后的操作数
|
||||
output reg [31:0] src1_o,
|
||||
output reg [31:0] src2_o
|
||||
);
|
||||
wire ex_mem_forward_valid = exmem_valid_i && exmem_reg_write_i &&
|
||||
!exmem_mem_to_reg_i && (exmem_rd_i != 5'd0);
|
||||
wire wb_forward_valid = memwb_valid_i && memwb_reg_write_i && (memwb_rd_i != 5'd0);
|
||||
|
||||
always @* begin
|
||||
src1_o = rs1_value_i;
|
||||
src2_o = rs2_value_i;
|
||||
|
||||
if (ex_mem_forward_valid && (exmem_rd_i == rs1_idx_i)) src1_o = exmem_value_i;
|
||||
else if (wb_forward_valid && (memwb_rd_i == rs1_idx_i)) src1_o = memwb_value_i;
|
||||
|
||||
if (ex_mem_forward_valid && (exmem_rd_i == rs2_idx_i)) src2_o = exmem_value_i;
|
||||
else if (wb_forward_valid && (memwb_rd_i == rs2_idx_i)) src2_o = memwb_value_i;
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,46 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// 冒险/流水控制单元。
|
||||
//
|
||||
// load-use 冒险：EX 级是 load 且 ID 级指令马上要用它的结果时，插入一个
|
||||
// 气泡（停顿一拍）。其余数据相关由前递网络解决。
|
||||
// 冲刷（flush_younger）优先级高于停顿：中断、URET、ecall 停机、分支
|
||||
// 重定向都会丢弃年轻指令，此时不需要再插气泡。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_hazard_unit (
|
||||
input wire ifid_valid_i,
|
||||
input wire idex_valid_i,
|
||||
input wire idex_mem_to_reg_i,
|
||||
input wire [4:0] idex_rd_i,
|
||||
input wire d_uses_rs1_i,
|
||||
input wire d_uses_rs2_i,
|
||||
input wire [4:0] d_src1_idx_i,
|
||||
input wire [4:0] d_src2_idx_i,
|
||||
// 冲刷来源
|
||||
input wire take_irq_i,
|
||||
input wire uret_redirect_i,
|
||||
input wire halt_event_i,
|
||||
input wire redirect_valid_i,
|
||||
input wire halted_i,
|
||||
// 控制结果
|
||||
output wire load_use_hazard_o,
|
||||
output wire flush_younger_o,
|
||||
output wire pipeline_stall_o
|
||||
);
|
||||
// EX 级为 load，且 ID 级的源寄存器与它的目的寄存器相同。
|
||||
assign load_use_hazard_o = ifid_valid_i && idex_valid_i && idex_mem_to_reg_i &&
|
||||
(idex_rd_i != 5'd0) &&
|
||||
((d_uses_rs1_i && (d_src1_idx_i == idex_rd_i)) ||
|
||||
(d_uses_rs2_i && (d_src2_idx_i == idex_rd_i)));
|
||||
|
||||
assign flush_younger_o = take_irq_i || uret_redirect_i || halt_event_i || redirect_valid_i;
|
||||
|
||||
// 停顿条件里不再包含 flush_younger：冲刷时 valid 位会被清 0、PC/IF-ID 也由
|
||||
// 冲刷分支（优先级高于停顿）处理，同时发生停顿只会多保持一拍 payload，
|
||||
// 不影响正确性。这样可以避免把“冲刷”这条长路径引到 payload 的时钟使能上。
|
||||
assign pipeline_stall_o = load_use_hazard_o && !halted_i;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,188 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// 中断控制器 + ustatus/uepc CSR + 嵌套返回栈。
|
||||
//
|
||||
// IRQ3 优先级最高，其次 IRQ2，最后 IRQ1；嵌套请求只有优先级高于当前级别
|
||||
// 才会被接纳。中断入口地址由优先级选出，返回地址保存在 epc_stack 中，
|
||||
// 当前上下文的活动返回 PC 放在 uepc_q（与课程讲义用 CSRRW 保存/恢复
|
||||
// uepc 的流程一致）。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_irq_ctrl #(
|
||||
parameter [31:0] IRQ1_VECTOR = 32'h0000_30ac,
|
||||
parameter [31:0] IRQ2_VECTOR = 32'h0000_31e4,
|
||||
parameter [31:0] IRQ3_VECTOR = 32'h0000_3310,
|
||||
parameter IRQ_STACK_DEPTH = 4,
|
||||
// ustatus 复位值。bit0 为 MIE。课程的中断测试程序只会在中断处理
|
||||
// 程序中设置 MIE，若复位后不立即置位 MIE，主程序将永远无法响应
|
||||
// 第一次中断，因此这里默认打开 MIE。
|
||||
parameter [31:0] USTATUS_INIT = 32'h0000_0001
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [ 2:0] irq_i,
|
||||
input wire halted_i,
|
||||
// EX 级正在处理重定向/URET/停机，此时不允许响应中断
|
||||
input wire ex_block_i,
|
||||
// 中断发生时要保存的返回地址（由顶层根据流水线状态给出）
|
||||
input wire [31:0] save_pc_i,
|
||||
// EX 级的 URET
|
||||
input wire uret_i,
|
||||
// EX 级 CSR 指令（CSRRW/CSRRSI/CSRRCI）
|
||||
input wire csr_valid_i,
|
||||
input wire csr_set_i,
|
||||
input wire csr_clear_i,
|
||||
input wire csr_write_i,
|
||||
input wire [11:0] csr_addr_i,
|
||||
input wire [31:0] csr_imm_i,
|
||||
input wire [31:0] csr_wdata_i,
|
||||
// 控制结果
|
||||
output wire take_irq_o,
|
||||
output wire [31:0] vector_o,
|
||||
output wire [31:0] return_pc_o,
|
||||
output wire [ 2:0] pending_o,
|
||||
output wire [ 1:0] level_o,
|
||||
output wire [31:0] uepc_o,
|
||||
output wire [31:0] ustatus_o
|
||||
);
|
||||
reg [31:0] ustatus_q;
|
||||
reg [31:0] uepc_q;
|
||||
reg [ 1:0] irq_current_q;
|
||||
reg [ 2:0] irq_pending_q;
|
||||
reg [ 2:0] irq_sync1_q;
|
||||
reg [ 2:0] irq_sync2_q;
|
||||
reg [ 2:0] irq_prev_q;
|
||||
reg [31:0] epc_stack [0:IRQ_STACK_DEPTH-1];
|
||||
reg [31:0] status_stack [0:IRQ_STACK_DEPTH-1];
|
||||
reg [ 1:0] priority_stack [0:IRQ_STACK_DEPTH-1];
|
||||
reg [ 2:0] irq_depth_q;
|
||||
|
||||
reg irq_selected_valid;
|
||||
reg [ 1:0] irq_selected_level;
|
||||
reg [31:0] irq_vector;
|
||||
reg [ 2:0] irq_pending_d;
|
||||
reg [31:0] ustatus_d;
|
||||
reg [31:0] uepc_d;
|
||||
|
||||
integer s;
|
||||
|
||||
// 上升沿检测：只在 irq_i 由 0 变 1 的那一拍产生中断事件。
|
||||
wire [ 2:0] irq_event = irq_sync2_q & ~irq_prev_q;
|
||||
|
||||
// 优先级仲裁：在当前级别允许的条件下选出优先级最高的中断源。
|
||||
always @* begin
|
||||
irq_selected_valid = 1'b0;
|
||||
irq_selected_level = 2'd0;
|
||||
if (irq_pending_q[2] && (irq_current_q < 2'd3)) begin
|
||||
irq_selected_valid = 1'b1;
|
||||
irq_selected_level = 2'd3;
|
||||
end else if (irq_pending_q[1] && (irq_current_q < 2'd2)) begin
|
||||
irq_selected_valid = 1'b1;
|
||||
irq_selected_level = 2'd2;
|
||||
end else if (irq_pending_q[0] && (irq_current_q < 2'd1)) begin
|
||||
irq_selected_valid = 1'b1;
|
||||
irq_selected_level = 2'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// 依据被选中的优先级选择对应的中断入口地址。
|
||||
always @* begin
|
||||
case (irq_selected_level)
|
||||
2'd1: irq_vector = IRQ1_VECTOR;
|
||||
2'd2: irq_vector = IRQ2_VECTOR;
|
||||
2'd3: irq_vector = IRQ3_VECTOR;
|
||||
default: irq_vector = IRQ1_VECTOR;
|
||||
endcase
|
||||
end
|
||||
|
||||
// 响应中断的条件：有已选中中断、MIE 使能、栈未溢出、未停机，且没有
|
||||
// 正在处理的重定向/URET/停机事件。
|
||||
assign take_irq_o = irq_selected_valid && ustatus_q[0] &&
|
||||
(irq_depth_q < IRQ_STACK_DEPTH) && !halted_i &&
|
||||
!ex_block_i;
|
||||
|
||||
assign vector_o = irq_vector;
|
||||
assign return_pc_o = uepc_q;
|
||||
assign pending_o = irq_pending_q;
|
||||
assign level_o = irq_current_q;
|
||||
assign uepc_o = uepc_q;
|
||||
assign ustatus_o = ustatus_q;
|
||||
|
||||
// 组合逻辑计算下一拍的挂起位与 CSR（ustatus/uepc）取值。
|
||||
always @* begin
|
||||
irq_pending_d = irq_pending_q | irq_event;
|
||||
if (take_irq_o) begin
|
||||
case (irq_selected_level)
|
||||
2'd1: irq_pending_d[0] = 1'b0;
|
||||
2'd2: irq_pending_d[1] = 1'b0;
|
||||
2'd3: irq_pending_d[2] = 1'b0;
|
||||
default: irq_pending_d = irq_pending_d;
|
||||
endcase
|
||||
end
|
||||
|
||||
ustatus_d = ustatus_q;
|
||||
uepc_d = uepc_q;
|
||||
if (csr_valid_i && csr_set_i) begin
|
||||
if (csr_addr_i == 12'h004) ustatus_d = ustatus_q | csr_imm_i;
|
||||
else if (csr_addr_i == 12'h041) uepc_d = uepc_q | csr_imm_i;
|
||||
end else if (csr_valid_i && csr_clear_i) begin
|
||||
if (csr_addr_i == 12'h004) ustatus_d = ustatus_q & ~csr_imm_i;
|
||||
else if (csr_addr_i == 12'h041) uepc_d = uepc_q & ~csr_imm_i;
|
||||
end else if (csr_valid_i && csr_write_i) begin
|
||||
if (csr_addr_i == 12'h004) ustatus_d = csr_wdata_i;
|
||||
else if (csr_addr_i == 12'h041) uepc_d = csr_wdata_i;
|
||||
end
|
||||
|
||||
if (take_irq_o) ustatus_d[0] = 1'b0;
|
||||
else if (uret_i && (irq_depth_q != 0)) ustatus_d = status_stack[irq_depth_q-1'b1];
|
||||
|
||||
if (take_irq_o) uepc_d = save_pc_i;
|
||||
else if (uret_i && (irq_depth_q > 1)) uepc_d = epc_stack[irq_depth_q-2];
|
||||
else if (uret_i && (irq_depth_q == 1)) uepc_d = 32'b0;
|
||||
end
|
||||
|
||||
// 复位时清空中断状态与嵌套栈。
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
ustatus_q <= USTATUS_INIT;
|
||||
uepc_q <= 32'b0;
|
||||
irq_current_q <= 2'b0;
|
||||
irq_pending_q <= 3'b0;
|
||||
irq_sync1_q <= 3'b0;
|
||||
irq_sync2_q <= 3'b0;
|
||||
irq_prev_q <= 3'b0;
|
||||
irq_depth_q <= 3'b0;
|
||||
for (s = 0; s < IRQ_STACK_DEPTH; s = s + 1) begin
|
||||
epc_stack[s] <= 32'b0;
|
||||
status_stack[s] <= 32'b0;
|
||||
priority_stack[s] <= 2'b0;
|
||||
end
|
||||
end else begin
|
||||
// 中断输入打两拍同步，并锁存挂起状态与 CSR。
|
||||
irq_sync1_q <= irq_i;
|
||||
irq_sync2_q <= irq_sync1_q;
|
||||
irq_prev_q <= irq_sync2_q;
|
||||
irq_pending_q <= irq_pending_d;
|
||||
ustatus_q <= ustatus_d;
|
||||
uepc_q <= uepc_d;
|
||||
|
||||
if (take_irq_o) begin
|
||||
if (irq_depth_q < IRQ_STACK_DEPTH) begin
|
||||
epc_stack[irq_depth_q] <= save_pc_i;
|
||||
status_stack[irq_depth_q] <= ustatus_q;
|
||||
priority_stack[irq_depth_q] <= irq_current_q;
|
||||
irq_depth_q <= irq_depth_q + 3'd1;
|
||||
end
|
||||
irq_current_q <= irq_selected_level;
|
||||
end else if (uret_i) begin
|
||||
if (irq_depth_q != 0) begin
|
||||
irq_depth_q <= irq_depth_q - 3'd1;
|
||||
irq_current_q <= priority_stack[irq_depth_q-1'b1];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,169 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// 多周期乘除法单元（时序逻辑，32 拍迭代）
|
||||
//
|
||||
// 原来乘除法直接写在 ALU 里（组合的 a*b / a%b）：综合后关键路径约 94 ns
|
||||
// （325 级逻辑、286 个 CARRY4），100 MHz 下无法收敛，只能把板上 100 MHz 分频
|
||||
// 到 6.25 MHz 再跑。这里改成移位迭代：
|
||||
// * 乘法：32 拍移位加法得到 64 位乘积；有符号变体先取操作数绝对值，
|
||||
// 迭代结束后按符号对 64 位乘积取负。
|
||||
// * 除法：32 拍恢复余数法得到商与余数；除零按 RISC-V 约定处理
|
||||
// （商为全 1、余数为被除数）。DIVU/REMU 都是无符号运算，不需要符号修正。
|
||||
//
|
||||
// 顶层的 EX 级会停留若干拍（往 EX/MEM 插气泡）等待 done_o 有效，然后照常写回。
|
||||
// 迭代期间顶层会屏蔽中断，避免在结果未定型时提前推进流水线。
|
||||
//
|
||||
// op_i 编码（由 cpu21_riscv_decoder 给出，MD_NONE 表示不是乘除法指令）：
|
||||
// MD_MUL mul ：无符号乘积低 32 位（有符号乘法的低 32 位与之相同）
|
||||
// MD_MULH mulh ：有符号 x 有符号，取高 32 位
|
||||
// MD_MULHSU mulhsu ：有符号 x 无符号，取高 32 位
|
||||
// MD_MULHU mulhu ：无符号 x 无符号，取高 32 位
|
||||
// MD_DIVU divu ：无符号商
|
||||
// MD_REMU remu ：无符号余数
|
||||
//
|
||||
// result_o / result2_o 的含义与原来的 ALU 保持一致：乘法时 result_o 为低 32 位、
|
||||
// result2_o 为高 32 位；除法时 result_o 为商、result2_o 为余数。译码器用 wb_sel
|
||||
// 决定写回哪一个（mulhu、remu 用 wb_sel=3 取 result2），因此顶层只需把这一对
|
||||
// 结果接到原来的 EX 结果总线上，其余流水逻辑不用改。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_muldiv (
|
||||
input wire clk,
|
||||
input wire reset, // 异步复位，高有效（与顶层一致）
|
||||
input wire start_i, // 指令在 EX 级且是乘除法（电平，模块内部只在空闲时响应）
|
||||
input wire [2:0] op_i, // 乘除法操作类型
|
||||
input wire [31:0] a_i, // EX 级 src1
|
||||
input wire [31:0] b_i, // EX 级 src2（ALU 的 B 端）
|
||||
output wire busy_o, // 迭代中（不含结果定型那一拍）
|
||||
output wire done_o, // 结果有效（单拍，此时顶层推进流水线）
|
||||
output wire [31:0] result_o, // 主结果
|
||||
output wire [31:0] result2_o // 第二结果（乘法高 32 位 / 除法余数）
|
||||
);
|
||||
localparam [2:0] MD_NONE = 3'd0;
|
||||
localparam [2:0] MD_MUL = 3'd1;
|
||||
localparam [2:0] MD_MULH = 3'd2;
|
||||
localparam [2:0] MD_MULHSU = 3'd3;
|
||||
localparam [2:0] MD_MULHU = 3'd4;
|
||||
localparam [2:0] MD_DIVU = 3'd5;
|
||||
localparam [2:0] MD_REMU = 3'd6;
|
||||
|
||||
localparam [1:0] S_IDLE = 2'd0;
|
||||
localparam [1:0] S_RUN = 2'd1;
|
||||
localparam [1:0] S_DONE = 2'd2;
|
||||
|
||||
reg [ 1:0] state_q;
|
||||
reg [ 5:0] cnt_q; // 0..32：0..31 为迭代，32 为结果定型
|
||||
reg [ 2:0] op_q;
|
||||
reg is_div_q;
|
||||
|
||||
// 乘法数据通路：64 位被乘数（每拍左移）、32 位乘数（每拍右移）、64 位累加器。
|
||||
reg [63:0] mcand_q;
|
||||
reg [31:0] mplier_q;
|
||||
reg [63:0] prod_q;
|
||||
reg sign_q;
|
||||
|
||||
// 除法数据通路：32 位除数、32 位商/被除数移位寄存器、33 位余数。
|
||||
reg [31:0] dvsr_q;
|
||||
reg [31:0] quo_q;
|
||||
reg [32:0] rem_q;
|
||||
reg [31:0] dvd_q; // 原始被除数（除零时原样返回）
|
||||
reg div_zero_q;
|
||||
|
||||
// 结果寄存器。
|
||||
reg [31:0] res_q;
|
||||
reg [31:0] res2_q;
|
||||
|
||||
assign busy_o = (state_q == S_RUN);
|
||||
assign done_o = (state_q == S_DONE);
|
||||
assign result_o = res_q;
|
||||
assign result2_o = res2_q;
|
||||
|
||||
// 乘法操作数准备：按操作类型决定是否取绝对值，并给出结果符号。
|
||||
wire a_signed = (op_i == MD_MULH) || (op_i == MD_MULHSU);
|
||||
wire b_signed = (op_i == MD_MULH);
|
||||
wire [31:0] a_mag = (a_signed && a_i[31]) ? (~a_i + 32'd1) : a_i;
|
||||
wire [31:0] b_mag = (b_signed && b_i[31]) ? (~b_i + 32'd1) : b_i;
|
||||
wire sign_in = ((op_i == MD_MULH) && (a_i[31] ^ b_i[31])) || ((op_i == MD_MULHSU) && a_i[31]);
|
||||
|
||||
// 除法的一步（恢复余数法）：把被除数最高位移进余数，够减则减并把商位置 1。
|
||||
wire [32:0] rem_shift = {rem_q[31:0], quo_q[31]};
|
||||
wire rem_ge = (rem_shift >= {1'b0, dvsr_q});
|
||||
wire [32:0] rem_next = rem_ge ? (rem_shift - {1'b0, dvsr_q}) : rem_shift;
|
||||
wire [31:0] quo_next = {quo_q[30:0], rem_ge};
|
||||
|
||||
// 迭代结束时的符号修正：prod_mag 为无符号乘积，sign_q 为 1 时取负。
|
||||
wire [63:0] prod_fix = sign_q ? (~prod_q + 64'd1) : prod_q;
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
state_q <= S_IDLE;
|
||||
cnt_q <= 6'd0;
|
||||
op_q <= MD_NONE;
|
||||
is_div_q <= 1'b0;
|
||||
mcand_q <= 64'd0;
|
||||
mplier_q <= 32'd0;
|
||||
prod_q <= 64'd0;
|
||||
sign_q <= 1'b0;
|
||||
dvsr_q <= 32'd0;
|
||||
quo_q <= 32'd0;
|
||||
rem_q <= 33'd0;
|
||||
dvd_q <= 32'd0;
|
||||
div_zero_q <= 1'b0;
|
||||
res_q <= 32'd0;
|
||||
res2_q <= 32'd0;
|
||||
end else begin
|
||||
case (state_q)
|
||||
// 空闲：指令进入 EX 且是乘除法时装载操作数，下一拍开始迭代。
|
||||
S_IDLE: begin
|
||||
if (start_i) begin
|
||||
state_q <= S_RUN;
|
||||
cnt_q <= 6'd0;
|
||||
op_q <= op_i;
|
||||
is_div_q <= (op_i == MD_DIVU) || (op_i == MD_REMU);
|
||||
// 乘法初始化（先取绝对值，符号留到最后修正）。
|
||||
mcand_q <= {32'b0, a_mag};
|
||||
mplier_q <= b_mag;
|
||||
prod_q <= 64'd0;
|
||||
sign_q <= sign_in;
|
||||
// 除法初始化（无符号）。
|
||||
dvsr_q <= b_i;
|
||||
quo_q <= a_i;
|
||||
rem_q <= 33'd0;
|
||||
dvd_q <= a_i;
|
||||
div_zero_q <= (b_i == 32'd0);
|
||||
end
|
||||
end
|
||||
|
||||
// 迭代：cnt 0..31 各走一步，32 拍后把结果定型。
|
||||
S_RUN: begin
|
||||
if (cnt_q == 6'd32) begin
|
||||
state_q <= S_DONE;
|
||||
if (is_div_q) begin
|
||||
res_q <= div_zero_q ? 32'hffff_ffff : quo_q;
|
||||
res2_q <= div_zero_q ? dvd_q : rem_q[31:0];
|
||||
end else begin
|
||||
res_q <= (op_q == MD_MULHU || op_q == MD_MUL) ? prod_fix[31:0] : prod_fix[63:32];
|
||||
res2_q <= prod_fix[63:32];
|
||||
end
|
||||
end else begin
|
||||
cnt_q <= cnt_q + 6'd1;
|
||||
if (is_div_q) begin
|
||||
rem_q <= rem_next;
|
||||
quo_q <= quo_next;
|
||||
end else begin
|
||||
prod_q <= mplier_q[0] ? (prod_q + mcand_q) : prod_q;
|
||||
mcand_q <= {mcand_q[62:0], 1'b0};
|
||||
mplier_q <= {1'b0, mplier_q[31:1]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 结果有效一拍，顶层据此推进流水线；随后回到空闲。
|
||||
default: state_q <= S_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,76 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// 性能计数器：周期数、停顿/气泡数、条件分支跳转数、无条件跳转数，
|
||||
// 以及分支预测的成功/失败次数。
|
||||
//
|
||||
// 这些计数器只影响可观测的统计量，不参与处理器控制，便于在波形中单独
|
||||
// 观察流水线效率。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_perf_counters (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire inc_cycle_i, // 未停机时周期数 +1
|
||||
input wire stall_i, // load-use 停顿或多周期乘除法停留
|
||||
input wire flush_i, // 冲刷年轻指令
|
||||
input wire cond_taken_i, // EX 级条件分支实际跳转
|
||||
input wire cond_valid_i, // EX 级条件分支有效
|
||||
input wire mispredict_i, // EX 级条件分支预测失败
|
||||
input wire uncond_i, // EX 级 JAL/JALR
|
||||
output wire [15:0] cycle_count_o,
|
||||
output wire [15:0] stall_count_o,
|
||||
output wire [15:0] bubble_count_o,
|
||||
output wire [15:0] conditional_taken_count_o,
|
||||
output wire [15:0] unconditional_branch_count_o,
|
||||
output wire [15:0] prediction_success_count_o,
|
||||
output wire [15:0] prediction_failure_count_o
|
||||
);
|
||||
reg [15:0] cycle_count_q;
|
||||
reg [15:0] stall_count_q;
|
||||
reg [15:0] bubble_count_q;
|
||||
reg [15:0] conditional_taken_count_q;
|
||||
reg [15:0] unconditional_branch_count_q;
|
||||
reg [15:0] prediction_success_count_q;
|
||||
reg [15:0] prediction_failure_count_q;
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cycle_count_q <= 16'b0;
|
||||
stall_count_q <= 16'b0;
|
||||
bubble_count_q <= 16'b0;
|
||||
conditional_taken_count_q <= 16'b0;
|
||||
unconditional_branch_count_q <= 16'b0;
|
||||
prediction_success_count_q <= 16'b0;
|
||||
prediction_failure_count_q <= 16'b0;
|
||||
end else begin
|
||||
if (inc_cycle_i) cycle_count_q <= cycle_count_q + 16'd1;
|
||||
|
||||
if (stall_i) begin
|
||||
stall_count_q <= stall_count_q + 16'd1;
|
||||
bubble_count_q <= bubble_count_q + 16'd1;
|
||||
end else if (flush_i) begin
|
||||
// 一次冲刷丢弃 IF/ID 两条年轻指令，记两个气泡。
|
||||
bubble_count_q <= bubble_count_q + 16'd2;
|
||||
end
|
||||
|
||||
if (cond_taken_i) conditional_taken_count_q <= conditional_taken_count_q + 16'd1;
|
||||
if (uncond_i) unconditional_branch_count_q <= unconditional_branch_count_q + 16'd1;
|
||||
|
||||
if (cond_valid_i) begin
|
||||
if (mispredict_i) prediction_failure_count_q <= prediction_failure_count_q + 16'd1;
|
||||
else prediction_success_count_q <= prediction_success_count_q + 16'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cycle_count_o = cycle_count_q;
|
||||
assign stall_count_o = stall_count_q;
|
||||
assign bubble_count_o = bubble_count_q;
|
||||
assign conditional_taken_count_o = conditional_taken_count_q;
|
||||
assign unconditional_branch_count_o = unconditional_branch_count_q;
|
||||
assign prediction_success_count_o = prediction_success_count_q;
|
||||
assign prediction_failure_count_o = prediction_failure_count_q;
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,843 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// cpu21-risc-v-4.circ -> 可综合 Verilog 实现（顶层）
|
||||
//
|
||||
// 处理器为五级流水线 IF/ID/EX/MEM/WB。本文件只保留：
|
||||
// * 五级流水寄存器与各级之间的连线；
|
||||
// * 各功能子模块的例化；
|
||||
// * PC / IF-ID / ID-EX 的控制优先级（中断、URET、停机、重定向、停顿、
|
||||
// 正常推进）；
|
||||
// * 对外输出与调试信号。
|
||||
//
|
||||
// 各功能单元已拆分为独立文件，便于单独仿真调试：
|
||||
// cpu21_riscv_alu.v 组合 ALU（result2 用于 MUL 高位 / 余数）
|
||||
// cpu21_bpb_8.v 八表项全相联分支目标缓冲
|
||||
// cpu21_riscv_decoder.v ID 级组合译码器
|
||||
// cpu21_riscv_regfile.v 寄存器堆（写优先旁路）
|
||||
// cpu21_riscv_forward_unit.v EX 级前递网络
|
||||
// cpu21_riscv_store_unit.v EX 级存储数据对齐
|
||||
// cpu21_riscv_branch_unit.v EX 级控制流裁决
|
||||
// cpu21_riscv_hazard_unit.v load-use 冒险与冲刷/停顿判定
|
||||
// cpu21_riscv_irq_ctrl.v 中断控制、ustatus/uepc 与嵌套返回栈
|
||||
// cpu21_riscv_perf_counters.v 性能计数器
|
||||
// cpu21_mmio.v MMIO：LED 数据寄存器（可写、可读回）
|
||||
//
|
||||
// 主要特性：
|
||||
// * EX 级前递（forwarding）与 load-use 冒险互锁；
|
||||
// * EX 级控制流裁决与流水线重定向；
|
||||
// * 八表项全相联分支目标缓冲（BPB）；
|
||||
// * 三路采样的中断源，带优先级与可嵌套的 URET 返回；
|
||||
// * LED 显示通过 MMIO 完成：向 LED_ADDR（默认 0x0000_1000）存储即写 LED，
|
||||
// 也可以从该地址读回 LED 当前值；
|
||||
// * ecall 仍用于停机：a7==34 的历史“显示”调用保留为无操作，其余（如 a7=10）
|
||||
// 令流水线停机并等待 go_i。
|
||||
//
|
||||
// 存储器接口约定：
|
||||
// instr_addr_o 与 data_addr_o 均为字节地址。data_wstrb_o 是字节写掩码，
|
||||
// 因此外部字宽 RAM 可用 data_addr_o[11:2] 作为字索引，再依据
|
||||
// data_wstrb_o 完成字节合并。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_redirect_int_bpb #(
|
||||
parameter RESET_PC = 32'h0000_0000,
|
||||
parameter IRQ1_VECTOR = 32'h0000_30ac,
|
||||
parameter IRQ2_VECTOR = 32'h0000_31e4,
|
||||
parameter IRQ3_VECTOR = 32'h0000_3310,
|
||||
parameter IRQ_STACK_DEPTH = 4,
|
||||
// MMIO：LED 数据寄存器地址（默认 0x0000_1000，位于 4 KB 数据 RAM 之外）。
|
||||
parameter [31:0] LED_ADDR = 32'h0000_1000,
|
||||
// ustatus 复位值。详见 cpu21_riscv_irq_ctrl 中的说明。
|
||||
parameter [31:0] USTATUS_INIT = 32'h0000_0001
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [31:0] instr_i,
|
||||
input wire [31:0] data_rdata_i,
|
||||
input wire [ 2:0] irq_i,
|
||||
input wire go_i,
|
||||
|
||||
output wire [31:0] instr_addr_o,
|
||||
output wire [31:0] data_addr_o,
|
||||
output wire [31:0] data_wdata_o,
|
||||
output wire [ 3:0] data_wstrb_o,
|
||||
output wire data_we_o,
|
||||
|
||||
output wire [31:0] led_data_o,
|
||||
output wire led_valid_o,
|
||||
output wire [31:0] if_pc_o,
|
||||
output wire [31:0] id_pc_o,
|
||||
output wire [31:0] ex_pc_o,
|
||||
output wire [31:0] mem_pc_o,
|
||||
output wire [31:0] wb_pc_o,
|
||||
output wire [31:0] if_ir_o,
|
||||
output wire [31:0] id_ir_o,
|
||||
output wire [31:0] ex_ir_o,
|
||||
output wire [31:0] mem_ir_o,
|
||||
output wire [31:0] wb_ir_o,
|
||||
output wire [31:0] rdin_o,
|
||||
output wire [31:0] mdin_o,
|
||||
output wire reg_write_o,
|
||||
output wire mem_write_o,
|
||||
output wire halted_o,
|
||||
|
||||
output wire [ 2:0] irq_pending_o,
|
||||
output wire [ 1:0] irq_current_level_o,
|
||||
output wire [31:0] uepc_o,
|
||||
output wire [31:0] ustatus_o,
|
||||
output wire bpb_predict_hit_o,
|
||||
output wire bpb_predict_taken_o,
|
||||
output wire bpb_mispredict_o,
|
||||
|
||||
output wire [15:0] cycle_count_o,
|
||||
output wire [15:0] stall_count_o,
|
||||
output wire [15:0] bubble_count_o,
|
||||
output wire [15:0] conditional_taken_count_o,
|
||||
output wire [15:0] unconditional_branch_count_o,
|
||||
output wire [15:0] prediction_success_count_o,
|
||||
output wire [15:0] prediction_failure_count_o
|
||||
);
|
||||
// 顶层只用到少量常量，完整译码表见 cpu21_riscv_decoder.v。
|
||||
localparam OP_BRANCH = 5'h18;
|
||||
localparam ALU_ADD = 4'd5;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 流水线寄存器
|
||||
// -------------------------------------------------------------------------
|
||||
// 当前取指 PC。
|
||||
reg [31:0] pc_q;
|
||||
|
||||
// IF/ID 流水寄存器（含本条指令所携带的分支预测信息）。
|
||||
reg ifid_valid_q;
|
||||
reg [31:0] ifid_pc_q;
|
||||
reg [31:0] ifid_ir_q;
|
||||
reg ifid_pred_taken_q;
|
||||
reg [31:0] ifid_pred_target_q;
|
||||
|
||||
// ID/EX 流水寄存器：保存译码结果与操作数。
|
||||
reg idex_valid_q;
|
||||
reg [31:0] idex_pc_q;
|
||||
reg [31:0] idex_ir_q;
|
||||
reg [31:0] idex_rs1_value_q;
|
||||
reg [31:0] idex_rs2_value_q;
|
||||
reg [4:0] idex_rs1_idx_q;
|
||||
reg [4:0] idex_rs2_idx_q;
|
||||
reg [4:0] idex_rd_q;
|
||||
reg [31:0] idex_imm_q;
|
||||
reg [3:0] idex_aluop_q;
|
||||
reg idex_alu_src_q;
|
||||
reg idex_reg_write_q;
|
||||
reg idex_mem_to_reg_q;
|
||||
reg idex_mem_write_q;
|
||||
reg idex_mem_byte_q;
|
||||
reg [2:0] idex_wb_sel_q;
|
||||
reg [2:0] idex_md_op_q; // 乘除法操作类型（0=非乘除法）
|
||||
reg [11:0] idex_csr_addr_q;
|
||||
reg idex_branch_q;
|
||||
reg idex_beq_q;
|
||||
reg idex_bne_q;
|
||||
reg idex_blt_q;
|
||||
reg idex_bge_q;
|
||||
reg idex_bltu_q;
|
||||
reg idex_bgeu_q;
|
||||
reg idex_jal_q;
|
||||
reg idex_jalr_q;
|
||||
reg idex_ecall_q;
|
||||
reg idex_uret_q;
|
||||
reg idex_csr_set_q;
|
||||
reg idex_csr_clear_q;
|
||||
reg idex_csr_write_q;
|
||||
reg idex_pred_taken_q;
|
||||
reg [31:0] idex_pred_target_q;
|
||||
|
||||
// EX/MEM 流水寄存器：保存 ALU/存储结果与写回控制。
|
||||
reg exmem_valid_q;
|
||||
reg [31:0] exmem_pc_q;
|
||||
reg [31:0] exmem_ir_q;
|
||||
reg [31:0] exmem_alu_result_q;
|
||||
reg [31:0] exmem_alu_result2_q;
|
||||
reg [31:0] exmem_csr_old_q;
|
||||
reg [31:0] exmem_write_data_q;
|
||||
reg [4:0] exmem_rd_q;
|
||||
reg exmem_reg_write_q;
|
||||
reg exmem_mem_to_reg_q;
|
||||
reg exmem_mem_write_q;
|
||||
reg [3:0] exmem_wstrb_q;
|
||||
reg [2:0] exmem_wb_sel_q;
|
||||
|
||||
// MEM/WB 流水寄存器：保存访存数据与最终写回信息。
|
||||
reg memwb_valid_q;
|
||||
reg [31:0] memwb_pc_q;
|
||||
reg [31:0] memwb_ir_q;
|
||||
reg [31:0] memwb_alu_result_q;
|
||||
reg [31:0] memwb_alu_result2_q;
|
||||
reg [31:0] memwb_csr_old_q;
|
||||
reg [31:0] memwb_mem_data_q;
|
||||
reg [4:0] memwb_rd_q;
|
||||
reg memwb_reg_write_q;
|
||||
reg memwb_mem_to_reg_q;
|
||||
reg [2:0] memwb_wb_sel_q;
|
||||
|
||||
// 停机标志（LED 寄存器已移入 cpu21_mmio.v）。
|
||||
reg halted_q;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// IF 级：分支预测。JAL/JALR 在 EX 级裁决，条件分支则可以直接依据 BPB
|
||||
// 给出的目标地址重定向取指 PC。
|
||||
// -------------------------------------------------------------------------
|
||||
wire [4:0] f_opcode = instr_i[6:2];
|
||||
wire [2:0] f_funct3 = instr_i[14:12];
|
||||
wire f_is_branch = (f_opcode == OP_BRANCH) &&
|
||||
((f_funct3 == 3'b000) || (f_funct3 == 3'b001) ||
|
||||
(f_funct3 == 3'b100) || (f_funct3 == 3'b101) ||
|
||||
(f_funct3 == 3'b110) || (f_funct3 == 3'b111));
|
||||
wire [31:0] bpb_predict_target;
|
||||
wire bpb_predict_hit;
|
||||
wire bpb_predict_taken;
|
||||
wire ex_branch_taken;
|
||||
wire [31:0] ex_target;
|
||||
wire ex_controlflow;
|
||||
wire ex_redirect_valid;
|
||||
wire [31:0] ex_redirect_pc;
|
||||
|
||||
// BPB 更新端口：在 EX 级用条件分支的实际结果训练预测器。
|
||||
wire bpb_update_enable = idex_valid_q && idex_branch_q;
|
||||
wire bpb_update_taken = ex_branch_taken;
|
||||
wire [31:0] bpb_update_target = ex_target;
|
||||
|
||||
// 分支目标缓冲实例。
|
||||
cpu21_bpb_8 u_bpb (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.predict_pc (pc_q),
|
||||
.predict_enable (f_is_branch),
|
||||
.predict_hit (bpb_predict_hit),
|
||||
.predict_taken (bpb_predict_taken),
|
||||
.predict_target (bpb_predict_target),
|
||||
.update_enable (bpb_update_enable),
|
||||
.update_controlflow(1'b1),
|
||||
.update_pc (idex_pc_q),
|
||||
.update_target (bpb_update_target),
|
||||
.update_taken (bpb_update_taken)
|
||||
);
|
||||
|
||||
// 下一取指 PC：预测跳转命中时使用 BPB 目标地址，否则顺序加 4。
|
||||
wire [31:0] fetch_next_pc =
|
||||
(f_is_branch && bpb_predict_hit && bpb_predict_taken) ?
|
||||
bpb_predict_target : (pc_q + 32'd4);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ID 级：译码与寄存器堆读取
|
||||
// -------------------------------------------------------------------------
|
||||
wire [4:0] d_src1_idx;
|
||||
wire [4:0] d_src2_idx;
|
||||
wire [4:0] d_rd;
|
||||
wire [31:0] d_imm;
|
||||
wire [3:0] d_aluop;
|
||||
wire [2:0] d_wb_sel;
|
||||
wire [2:0] d_md_op;
|
||||
wire [11:0] d_csr_addr;
|
||||
wire d_uses_rs1;
|
||||
wire d_uses_rs2;
|
||||
wire d_reg_write;
|
||||
wire d_mem_to_reg;
|
||||
wire d_mem_write;
|
||||
wire d_mem_byte;
|
||||
wire d_alu_src;
|
||||
wire d_branch;
|
||||
wire d_beq;
|
||||
wire d_bne;
|
||||
wire d_blt;
|
||||
wire d_bge;
|
||||
wire d_bltu;
|
||||
wire d_bgeu;
|
||||
wire d_jal;
|
||||
wire d_jalr;
|
||||
wire d_ecall;
|
||||
wire d_uret;
|
||||
wire d_csr_set;
|
||||
wire d_csr_clear;
|
||||
wire d_csr_write;
|
||||
|
||||
cpu21_riscv_decoder u_decoder (
|
||||
.ir_i (ifid_ir_q),
|
||||
.rs1_idx_o (d_src1_idx),
|
||||
.rs2_idx_o (d_src2_idx),
|
||||
.rd_o (d_rd),
|
||||
.imm_o (d_imm),
|
||||
.alu_op_o (d_aluop),
|
||||
.wb_sel_o (d_wb_sel),
|
||||
.md_op_o (d_md_op),
|
||||
.csr_addr_o (d_csr_addr),
|
||||
.uses_rs1_o (d_uses_rs1),
|
||||
.uses_rs2_o (d_uses_rs2),
|
||||
.reg_write_o (d_reg_write),
|
||||
.mem_to_reg_o(d_mem_to_reg),
|
||||
.mem_write_o (d_mem_write),
|
||||
.mem_byte_o (d_mem_byte),
|
||||
.alu_src_o (d_alu_src),
|
||||
.branch_o (d_branch),
|
||||
.beq_o (d_beq),
|
||||
.bne_o (d_bne),
|
||||
.blt_o (d_blt),
|
||||
.bge_o (d_bge),
|
||||
.bltu_o (d_bltu),
|
||||
.bgeu_o (d_bgeu),
|
||||
.jal_o (d_jal),
|
||||
.jalr_o (d_jalr),
|
||||
.ecall_o (d_ecall),
|
||||
.uret_o (d_uret),
|
||||
.csr_set_o (d_csr_set),
|
||||
.csr_clear_o (d_csr_clear),
|
||||
.csr_write_o (d_csr_write)
|
||||
);
|
||||
|
||||
// 写回值选择：wb_sel 0=ALU 结果，1=访存数据，2=PC+4（已存在 alu_result 里），
|
||||
// 3=MUL 高位/余数，4=CSR 旧值。
|
||||
wire [31:0] wb_value;
|
||||
assign wb_value = (memwb_wb_sel_q == 3'd1) ? memwb_mem_data_q :
|
||||
(memwb_wb_sel_q == 3'd3) ? memwb_alu_result2_q :
|
||||
(memwb_wb_sel_q == 3'd4) ? memwb_csr_old_q :
|
||||
memwb_alu_result_q;
|
||||
|
||||
// WB 级写回使能（同时用于寄存器堆的写端口与写优先旁路）。
|
||||
wire memwb_reg_write_en = memwb_valid_q && memwb_reg_write_q;
|
||||
|
||||
// ID 级读寄存器：x0 恒为 0，并对同周期 WB 的结果做写优先旁路。
|
||||
wire [31:0] d_rs1_value;
|
||||
wire [31:0] d_rs2_value;
|
||||
|
||||
cpu21_riscv_regfile u_regfile (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.rs1_idx_i (d_src1_idx),
|
||||
.rs2_idx_i (d_src2_idx),
|
||||
.rs1_data_o(d_rs1_value),
|
||||
.rs2_data_o(d_rs2_value),
|
||||
.we_i (memwb_reg_write_en),
|
||||
.waddr_i (memwb_rd_q),
|
||||
.wdata_i (wb_value)
|
||||
);
|
||||
|
||||
// 中断/CSR 相关连线（中断控制器实例见下方"中断 / CSR"小节）。
|
||||
wire take_irq;
|
||||
wire [31:0] irq_vector;
|
||||
wire [31:0] ex_return_pc;
|
||||
wire [2:0] irq_pending;
|
||||
wire [1:0] irq_current_level;
|
||||
wire [31:0] uepc_value;
|
||||
wire [31:0] ustatus_value;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// EX 级：前递网络、ALU 运算、存储对齐与控制流裁决
|
||||
// -------------------------------------------------------------------------
|
||||
// EX/MEM 级要前递的值（按 wb_sel 选取）。JAL/JALR 的链接地址（PC+4）已在
|
||||
// EX 级预先算好并存入 exmem_alu_result_q，所以这里 wb_sel=2 直接取该寄存器，
|
||||
// 前递路径上不再有 PC+4 加法器（100 MHz 下这是最长路径之一）。
|
||||
wire [31:0] exmem_forward_value =
|
||||
(exmem_wb_sel_q == 3'd3) ? exmem_alu_result2_q :
|
||||
(exmem_wb_sel_q == 3'd4) ? exmem_csr_old_q :
|
||||
exmem_alu_result_q;
|
||||
|
||||
// 前递优先级：EX/MEM 的结果最新，其次为 MEM/WB 写回值，最后才是
|
||||
// 译码时读到的寄存器值。
|
||||
wire [31:0] ex_src1;
|
||||
wire [31:0] ex_src2;
|
||||
|
||||
cpu21_riscv_forward_unit u_forward_unit (
|
||||
.rs1_value_i (idex_rs1_value_q),
|
||||
.rs2_value_i (idex_rs2_value_q),
|
||||
.rs1_idx_i (idex_rs1_idx_q),
|
||||
.rs2_idx_i (idex_rs2_idx_q),
|
||||
.exmem_valid_i (exmem_valid_q),
|
||||
.exmem_reg_write_i (exmem_reg_write_q),
|
||||
.exmem_mem_to_reg_i(exmem_mem_to_reg_q),
|
||||
.exmem_rd_i (exmem_rd_q),
|
||||
.exmem_value_i (exmem_forward_value),
|
||||
.memwb_valid_i (memwb_valid_q),
|
||||
.memwb_reg_write_i (memwb_reg_write_q),
|
||||
.memwb_rd_i (memwb_rd_q),
|
||||
.memwb_value_i (wb_value),
|
||||
.src1_o (ex_src1),
|
||||
.src2_o (ex_src2)
|
||||
);
|
||||
|
||||
// ALU 的 B 端：立即数或 rs2。
|
||||
wire [31:0] ex_alu_b = idex_alu_src_q ? idex_imm_q : ex_src2;
|
||||
wire [31:0] ex_alu_result;
|
||||
wire [31:0] ex_alu_result2;
|
||||
// 读取 CSR 旧值（ustatus=0x004、uepc=0x041），供 CSR 指令回写 rd。
|
||||
wire [31:0] ex_csr_old_value =
|
||||
(idex_csr_addr_q == 12'h004) ? ustatus_value :
|
||||
(idex_csr_addr_q == 12'h041) ? uepc_value : 32'b0;
|
||||
|
||||
// ALU 实例（只做单拍运算；乘除法见下面的多周期单元）。
|
||||
cpu21_riscv_alu u_ex_alu (
|
||||
.op (idex_aluop_q),
|
||||
.a (ex_src1),
|
||||
.b (ex_alu_b),
|
||||
.result (ex_alu_result),
|
||||
.result2(ex_alu_result2)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 多周期乘除法单元：EX 级停留若干拍等待结果，不再把 32x32 乘法/除法
|
||||
// 放在组合路径上（原来这部分的组合延时约 94 ns，100 MHz 下无法收敛）。
|
||||
// 指令在 EX 级期间 ex_md_stall 有效：ID/EX 保持不变、EX/MEM 插气泡、
|
||||
// 取指/译码冻结；迭代结束（md_done）后照常推进。
|
||||
// -------------------------------------------------------------------------
|
||||
wire md_busy;
|
||||
wire md_done;
|
||||
wire [31:0] md_result;
|
||||
wire [31:0] md_result2;
|
||||
|
||||
wire ex_is_muldiv = idex_valid_q && (idex_md_op_q != 3'd0);
|
||||
wire ex_md_stall = ex_is_muldiv && !md_done;
|
||||
|
||||
cpu21_riscv_muldiv u_muldiv (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.start_i (ex_is_muldiv),
|
||||
.op_i (idex_md_op_q),
|
||||
.a_i (ex_src1),
|
||||
.b_i (ex_alu_b),
|
||||
.busy_o (md_busy),
|
||||
.done_o (md_done),
|
||||
.result_o (md_result),
|
||||
.result2_o(md_result2)
|
||||
);
|
||||
|
||||
// EX 级最终结果：乘除法取多周期单元的输出；JAL/JALR（wb_sel=2）的链接地址
|
||||
// PC+4 在这里算好随流水寄存器传下去，避免“写回值 → 前递 → 停机判定 →
|
||||
// 流水寄存器时钟使能”这条组合路径上出现 32 位加法器。
|
||||
wire [31:0] ex_result =
|
||||
ex_is_muldiv ? md_result :
|
||||
(idex_wb_sel_q == 3'd2) ? (idex_pc_q + 32'd4) :
|
||||
ex_alu_result;
|
||||
wire [31:0] ex_result2 = ex_is_muldiv ? md_result2 : ex_alu_result2;
|
||||
|
||||
// 控制流裁决：条件分支方向/目标、JAL/JALR 目标、是否需要重定向。
|
||||
cpu21_riscv_branch_unit u_branch_unit (
|
||||
.valid_i (idex_valid_q),
|
||||
.pc_i (idex_pc_q),
|
||||
.imm_i (idex_imm_q),
|
||||
.src1_i (ex_src1),
|
||||
.src2_i (ex_src2),
|
||||
.branch_i (idex_branch_q),
|
||||
.beq_i (idex_beq_q),
|
||||
.bne_i (idex_bne_q),
|
||||
.blt_i (idex_blt_q),
|
||||
.bge_i (idex_bge_q),
|
||||
.bltu_i (idex_bltu_q),
|
||||
.bgeu_i (idex_bgeu_q),
|
||||
.jal_i (idex_jal_q),
|
||||
.jalr_i (idex_jalr_q),
|
||||
.pred_taken_i (idex_pred_taken_q),
|
||||
.pred_target_i (idex_pred_target_q),
|
||||
.branch_taken_o (ex_branch_taken),
|
||||
.controlflow_o (ex_controlflow),
|
||||
.target_o (ex_target),
|
||||
.redirect_valid_o(ex_redirect_valid),
|
||||
.redirect_pc_o (ex_redirect_pc)
|
||||
);
|
||||
|
||||
// 存储数据对齐：依据字节地址低两位生成写数据与字节写掩码。
|
||||
wire [31:0] ex_store_data;
|
||||
wire [ 3:0] ex_store_wstrb;
|
||||
|
||||
cpu21_riscv_store_unit u_store_unit (
|
||||
.addr_i (ex_alu_result),
|
||||
.data_i (ex_src2),
|
||||
.mem_write_i (idex_mem_write_q),
|
||||
.mem_byte_i (idex_mem_byte_q),
|
||||
.store_data_o (ex_store_data),
|
||||
.store_wstrb_o(ex_store_wstrb)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// MMIO：LED 等外设映射到数据地址空间，在 MEM 级做地址译码。
|
||||
// -------------------------------------------------------------------------
|
||||
wire [31:0] mmio_rdata;
|
||||
wire mmio_rdata_hit;
|
||||
|
||||
cpu21_mmio #(
|
||||
.LED_ADDR(LED_ADDR)
|
||||
) u_mmio (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.mem_valid_i(exmem_valid_q),
|
||||
.mem_write_i(exmem_mem_write_q),
|
||||
.mem_read_i (exmem_mem_to_reg_q),
|
||||
.addr_i (exmem_alu_result_q),
|
||||
.wdata_i (exmem_write_data_q),
|
||||
.wstrb_i (exmem_wstrb_q),
|
||||
.rdata_o (mmio_rdata),
|
||||
.rdata_hit_o(mmio_rdata_hit),
|
||||
.led_data_o (led_data_o),
|
||||
.led_valid_o(led_valid_o)
|
||||
);
|
||||
|
||||
// 访存读数据：命中 MMIO 时用外设数据，否则用外部存储器数据。
|
||||
wire [31:0] mem_rdata = mmio_rdata_hit ? mmio_rdata : data_rdata_i;
|
||||
|
||||
// ecall 约定：LED 显示已改由 MMIO 存储完成（见上方的 cpu21_mmio 例化）。
|
||||
// a7==34 的历史“显示”调用保留为无操作；其余（例如 a7=10）令处理器停机，
|
||||
// 等待 go_i 重新启动。
|
||||
wire ex_halt_event = idex_valid_q && idex_ecall_q && (ex_src1 != 32'd34);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 中断 / CSR / 嵌套返回栈
|
||||
// -------------------------------------------------------------------------
|
||||
wire ex_uret_redirect = idex_valid_q && idex_uret_q;
|
||||
// EX 级正在 URET，或乘除法还没算完时，不响应中断：前者与中断同时发生会丢掉
|
||||
// URET 的返回地址，后者会在结果未定型时推进流水线，向 rd 写回错误值。
|
||||
// 这里不再包含 ex_redirect_valid / ex_halt_event：它们本身就会让
|
||||
// flush_younger 有效（流水线照常被冲刷），而中断优先于重定向时返回地址由
|
||||
// irq_save_pc 给出（已正确跳转的分支取目标地址）。这样就把
|
||||
// “分支判决 → 中断控制器 → flush → 流水寄存器控制”这条 100 MHz 下的
|
||||
// 关键路径切断了（原来要绕经中断控制器再回到 flush）。
|
||||
wire ex_block_irq = ex_uret_redirect || ex_md_stall;
|
||||
// 中断发生时要保存的返回地址取"下一个架构 PC"：若 EX 是一条预测正确
|
||||
// 且已跳转的分支，则该 PC 就是它的目标地址；若 EX 为空，则 IF/ID 中
|
||||
// 保存的就是尚未执行的最老指令。
|
||||
wire [31:0] irq_save_pc = idex_valid_q ?
|
||||
((idex_branch_q && ex_branch_taken) ? ex_target : (idex_pc_q + 32'd4)) :
|
||||
(ifid_valid_q ? ifid_pc_q : pc_q);
|
||||
|
||||
|
||||
cpu21_riscv_irq_ctrl #(
|
||||
.IRQ1_VECTOR (IRQ1_VECTOR),
|
||||
.IRQ2_VECTOR (IRQ2_VECTOR),
|
||||
.IRQ3_VECTOR (IRQ3_VECTOR),
|
||||
.IRQ_STACK_DEPTH(IRQ_STACK_DEPTH),
|
||||
.USTATUS_INIT (USTATUS_INIT)
|
||||
) u_irq_ctrl (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.irq_i (irq_i),
|
||||
.halted_i (halted_q),
|
||||
.ex_block_i (ex_block_irq),
|
||||
.save_pc_i (irq_save_pc),
|
||||
.uret_i (ex_uret_redirect),
|
||||
.csr_valid_i(idex_valid_q),
|
||||
.csr_set_i (idex_csr_set_q),
|
||||
.csr_clear_i(idex_csr_clear_q),
|
||||
.csr_write_i(idex_csr_write_q),
|
||||
.csr_addr_i (idex_csr_addr_q),
|
||||
.csr_imm_i (idex_imm_q),
|
||||
.csr_wdata_i(ex_src1),
|
||||
.take_irq_o (take_irq),
|
||||
.vector_o (irq_vector),
|
||||
.return_pc_o(ex_return_pc),
|
||||
.pending_o (irq_pending),
|
||||
.level_o (irq_current_level),
|
||||
.uepc_o (uepc_value),
|
||||
.ustatus_o (ustatus_value)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 冒险 / 停顿 / 冲刷判定
|
||||
// -------------------------------------------------------------------------
|
||||
wire load_use_hazard;
|
||||
wire flush_younger;
|
||||
wire pipeline_stall;
|
||||
|
||||
cpu21_riscv_hazard_unit u_hazard_unit (
|
||||
.ifid_valid_i (ifid_valid_q),
|
||||
.idex_valid_i (idex_valid_q),
|
||||
.idex_mem_to_reg_i(idex_mem_to_reg_q),
|
||||
.idex_rd_i (idex_rd_q),
|
||||
.d_uses_rs1_i (d_uses_rs1),
|
||||
.d_uses_rs2_i (d_uses_rs2),
|
||||
.d_src1_idx_i (d_src1_idx),
|
||||
.d_src2_idx_i (d_src2_idx),
|
||||
.take_irq_i (take_irq),
|
||||
.uret_redirect_i (ex_uret_redirect),
|
||||
.halt_event_i (ex_halt_event),
|
||||
.redirect_valid_i (ex_redirect_valid),
|
||||
.halted_i (halted_q),
|
||||
.load_use_hazard_o(load_use_hazard),
|
||||
.flush_younger_o (flush_younger),
|
||||
.pipeline_stall_o (pipeline_stall)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 对外输出与调试信号。
|
||||
// -------------------------------------------------------------------------
|
||||
// 存储器接口：指令地址来自取指 PC；数据地址/写数据/写掩码来自 MEM 级。
|
||||
assign instr_addr_o = pc_q;
|
||||
assign data_addr_o = exmem_alu_result_q;
|
||||
assign data_wdata_o = exmem_write_data_q;
|
||||
assign data_wstrb_o = (exmem_valid_q && exmem_mem_write_q) ? exmem_wstrb_q : 4'b0;
|
||||
assign data_we_o = |data_wstrb_o;
|
||||
|
||||
// LED 输出由 cpu21_mmio 驱动，这里只保留流水线各级 PC/指令回显。
|
||||
assign if_pc_o = pc_q;
|
||||
assign id_pc_o = ifid_valid_q ? ifid_pc_q : 32'b0;
|
||||
assign ex_pc_o = idex_valid_q ? idex_pc_q : 32'b0;
|
||||
assign mem_pc_o = exmem_valid_q ? exmem_pc_q : 32'b0;
|
||||
assign wb_pc_o = memwb_valid_q ? memwb_pc_q : 32'b0;
|
||||
assign if_ir_o = instr_i;
|
||||
assign id_ir_o = ifid_valid_q ? ifid_ir_q : 32'b0;
|
||||
assign ex_ir_o = idex_valid_q ? idex_ir_q : 32'b0;
|
||||
assign mem_ir_o = exmem_valid_q ? exmem_ir_q : 32'b0;
|
||||
assign wb_ir_o = memwb_valid_q ? memwb_ir_q : 32'b0;
|
||||
assign rdin_o = wb_value;
|
||||
assign mdin_o = exmem_write_data_q;
|
||||
assign reg_write_o = memwb_valid_q && memwb_reg_write_q;
|
||||
assign mem_write_o = exmem_valid_q && exmem_mem_write_q;
|
||||
assign halted_o = halted_q;
|
||||
assign irq_pending_o = irq_pending;
|
||||
assign irq_current_level_o = irq_current_level;
|
||||
assign uepc_o = uepc_value;
|
||||
assign ustatus_o = ustatus_value;
|
||||
assign bpb_predict_hit_o = bpb_predict_hit;
|
||||
assign bpb_predict_taken_o = bpb_predict_taken;
|
||||
assign bpb_mispredict_o = ex_redirect_valid && idex_branch_q;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 状态更新。顺序遵循五级流水线：先捕获 MEM/WB、EX/MEM，再处理
|
||||
// ID/EX 与 IF/ID/PC 的控制。
|
||||
// -------------------------------------------------------------------------
|
||||
// 复位时清空所有流水寄存器与 LED/停机标志（寄存器堆、中断状态与
|
||||
// 性能计数器在各自的子模块内复位）。
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
pc_q <= RESET_PC;
|
||||
ifid_valid_q <= 1'b0;
|
||||
ifid_pc_q <= 32'b0;
|
||||
ifid_ir_q <= 32'b0;
|
||||
ifid_pred_taken_q <= 1'b0;
|
||||
ifid_pred_target_q <= 32'b0;
|
||||
|
||||
idex_valid_q <= 1'b0;
|
||||
idex_pc_q <= 32'b0;
|
||||
idex_ir_q <= 32'b0;
|
||||
idex_rs1_value_q <= 32'b0;
|
||||
idex_rs2_value_q <= 32'b0;
|
||||
idex_rs1_idx_q <= 5'b0;
|
||||
idex_rs2_idx_q <= 5'b0;
|
||||
idex_rd_q <= 5'b0;
|
||||
idex_imm_q <= 32'b0;
|
||||
idex_aluop_q <= ALU_ADD;
|
||||
idex_alu_src_q <= 1'b0;
|
||||
idex_reg_write_q <= 1'b0;
|
||||
idex_mem_to_reg_q <= 1'b0;
|
||||
idex_mem_write_q <= 1'b0;
|
||||
idex_mem_byte_q <= 1'b0;
|
||||
idex_wb_sel_q <= 3'b0;
|
||||
idex_md_op_q <= 3'b0;
|
||||
idex_csr_addr_q <= 12'b0;
|
||||
idex_branch_q <= 1'b0;
|
||||
idex_beq_q <= 1'b0;
|
||||
idex_bne_q <= 1'b0;
|
||||
idex_blt_q <= 1'b0;
|
||||
idex_bge_q <= 1'b0;
|
||||
idex_bltu_q <= 1'b0;
|
||||
idex_bgeu_q <= 1'b0;
|
||||
idex_jal_q <= 1'b0;
|
||||
idex_jalr_q <= 1'b0;
|
||||
idex_ecall_q <= 1'b0;
|
||||
idex_uret_q <= 1'b0;
|
||||
idex_csr_set_q <= 1'b0;
|
||||
idex_csr_clear_q <= 1'b0;
|
||||
idex_csr_write_q <= 1'b0;
|
||||
idex_pred_taken_q <= 1'b0;
|
||||
idex_pred_target_q <= 32'b0;
|
||||
|
||||
exmem_valid_q <= 1'b0;
|
||||
exmem_pc_q <= 32'b0;
|
||||
exmem_ir_q <= 32'b0;
|
||||
exmem_alu_result_q <= 32'b0;
|
||||
exmem_alu_result2_q <= 32'b0;
|
||||
exmem_csr_old_q <= 32'b0;
|
||||
exmem_write_data_q <= 32'b0;
|
||||
exmem_rd_q <= 5'b0;
|
||||
exmem_reg_write_q <= 1'b0;
|
||||
exmem_mem_to_reg_q <= 1'b0;
|
||||
exmem_mem_write_q <= 1'b0;
|
||||
exmem_wstrb_q <= 4'b0;
|
||||
exmem_wb_sel_q <= 3'b0;
|
||||
|
||||
memwb_valid_q <= 1'b0;
|
||||
memwb_pc_q <= 32'b0;
|
||||
memwb_ir_q <= 32'b0;
|
||||
memwb_alu_result_q <= 32'b0;
|
||||
memwb_alu_result2_q <= 32'b0;
|
||||
memwb_csr_old_q <= 32'b0;
|
||||
memwb_mem_data_q <= 32'b0;
|
||||
memwb_rd_q <= 5'b0;
|
||||
memwb_reg_write_q <= 1'b0;
|
||||
memwb_mem_to_reg_q <= 1'b0;
|
||||
memwb_wb_sel_q <= 3'b0;
|
||||
|
||||
halted_q <= 1'b0;
|
||||
end else begin
|
||||
if (go_i) halted_q <= 1'b0;
|
||||
if (ex_halt_event) halted_q <= 1'b1;
|
||||
|
||||
// MEM/WB 流水寄存器捕获。
|
||||
memwb_valid_q <= exmem_valid_q;
|
||||
memwb_pc_q <= exmem_pc_q;
|
||||
memwb_ir_q <= exmem_ir_q;
|
||||
memwb_alu_result_q <= exmem_alu_result_q;
|
||||
memwb_alu_result2_q <= exmem_alu_result2_q;
|
||||
memwb_csr_old_q <= exmem_csr_old_q;
|
||||
memwb_mem_data_q <= mem_rdata;
|
||||
memwb_rd_q <= exmem_rd_q;
|
||||
memwb_reg_write_q <= exmem_reg_write_q;
|
||||
memwb_mem_to_reg_q <= exmem_mem_to_reg_q;
|
||||
memwb_wb_sel_q <= exmem_wb_sel_q;
|
||||
|
||||
// EX/MEM 流水寄存器捕获。乘除法迭代期间（ex_md_stall）往 EX/MEM 插气泡，
|
||||
// 让乘除法指令继续占用 EX，结果在 md_done 那一拍才写入 EX/MEM。
|
||||
if (ex_md_stall) begin
|
||||
exmem_valid_q <= 1'b0;
|
||||
exmem_pc_q <= 32'b0;
|
||||
exmem_ir_q <= 32'b0;
|
||||
exmem_alu_result_q <= 32'b0;
|
||||
exmem_alu_result2_q <= 32'b0;
|
||||
exmem_csr_old_q <= 32'b0;
|
||||
exmem_write_data_q <= 32'b0;
|
||||
exmem_rd_q <= 5'b0;
|
||||
exmem_reg_write_q <= 1'b0;
|
||||
exmem_mem_to_reg_q <= 1'b0;
|
||||
exmem_mem_write_q <= 1'b0;
|
||||
exmem_wstrb_q <= 4'b0;
|
||||
exmem_wb_sel_q <= 3'b0;
|
||||
end else begin
|
||||
exmem_valid_q <= idex_valid_q;
|
||||
exmem_pc_q <= idex_pc_q;
|
||||
exmem_ir_q <= idex_ir_q;
|
||||
exmem_alu_result_q <= ex_result;
|
||||
exmem_alu_result2_q <= ex_result2;
|
||||
exmem_csr_old_q <= ex_csr_old_value;
|
||||
exmem_write_data_q <= ex_store_data;
|
||||
exmem_rd_q <= idex_rd_q;
|
||||
exmem_reg_write_q <= idex_reg_write_q;
|
||||
exmem_mem_to_reg_q <= idex_mem_to_reg_q;
|
||||
exmem_mem_write_q <= idex_mem_write_q;
|
||||
exmem_wstrb_q <= ex_store_wstrb;
|
||||
exmem_wb_sel_q <= idex_wb_sel_q;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ID/EX 装载。
|
||||
//
|
||||
// payload（PC/IR/控制位/预测位）只在 load-use 停顿、乘除法迭代、停机时
|
||||
// 保持（时钟使能与“冲刷”无关），其余情况一律装载；只有 valid 位受冲刷
|
||||
// 控制，冲刷时清 0。这样“EX 级组合判决（分支/中断）→ 流水寄存器时钟
|
||||
// 使能”这条 100 MHz 下最长的路径就只剩下一个触发器（valid），payload
|
||||
// 即使装进错误路径的数据也无害——所有使用者都以 idex_valid_q 为前提。
|
||||
// ---------------------------------------------------------------------
|
||||
if (!(pipeline_stall || halted_q || ex_md_stall)) begin
|
||||
idex_pc_q <= ifid_pc_q;
|
||||
idex_ir_q <= ifid_ir_q;
|
||||
idex_rs1_value_q <= d_rs1_value;
|
||||
idex_rs2_value_q <= d_rs2_value;
|
||||
idex_rs1_idx_q <= d_src1_idx;
|
||||
idex_rs2_idx_q <= d_src2_idx;
|
||||
idex_rd_q <= d_rd;
|
||||
idex_imm_q <= d_imm;
|
||||
idex_aluop_q <= d_aluop;
|
||||
idex_alu_src_q <= d_alu_src;
|
||||
idex_reg_write_q <= d_reg_write;
|
||||
idex_mem_to_reg_q <= d_mem_to_reg;
|
||||
idex_mem_write_q <= d_mem_write;
|
||||
idex_mem_byte_q <= d_mem_byte;
|
||||
idex_wb_sel_q <= d_wb_sel;
|
||||
idex_md_op_q <= d_md_op;
|
||||
idex_csr_addr_q <= d_csr_addr;
|
||||
idex_branch_q <= d_branch;
|
||||
idex_beq_q <= d_beq;
|
||||
idex_bne_q <= d_bne;
|
||||
idex_blt_q <= d_blt;
|
||||
idex_bge_q <= d_bge;
|
||||
idex_bltu_q <= d_bltu;
|
||||
idex_bgeu_q <= d_bgeu;
|
||||
idex_jal_q <= d_jal;
|
||||
idex_jalr_q <= d_jalr;
|
||||
idex_ecall_q <= d_ecall;
|
||||
idex_uret_q <= d_uret;
|
||||
idex_csr_set_q <= d_csr_set;
|
||||
idex_csr_clear_q <= d_csr_clear;
|
||||
idex_csr_write_q <= d_csr_write;
|
||||
idex_pred_taken_q <= ifid_pred_taken_q;
|
||||
idex_pred_target_q <= ifid_pred_target_q;
|
||||
end
|
||||
|
||||
if (halted_q || ex_md_stall) begin
|
||||
// 停机 / 乘除法迭代：valid 保持不变（指令继续占用 EX）。
|
||||
end else if (pipeline_stall || flush_younger) begin
|
||||
// load-use 停顿：load 已经进 EX/MEM，这里给 EX 装一个气泡（payload 保持
|
||||
// 原值，valid=0 时无害）；冲刷同理。
|
||||
idex_valid_q <= 1'b0;
|
||||
end else begin
|
||||
idex_valid_q <= ifid_valid_q;
|
||||
end
|
||||
|
||||
if (take_irq) begin
|
||||
pc_q <= irq_vector;
|
||||
ifid_valid_q <= 1'b0;
|
||||
ifid_pred_taken_q <= 1'b0;
|
||||
ifid_pred_target_q <= 32'b0;
|
||||
end else if (ex_uret_redirect) begin
|
||||
pc_q <= ex_return_pc;
|
||||
ifid_valid_q <= 1'b0;
|
||||
ifid_pred_taken_q <= 1'b0;
|
||||
ifid_pred_target_q <= 32'b0;
|
||||
end else if (ex_halt_event) begin
|
||||
pc_q <= idex_pc_q + 32'd4;
|
||||
ifid_valid_q <= 1'b0;
|
||||
ifid_pred_taken_q <= 1'b0;
|
||||
ifid_pred_target_q <= 32'b0;
|
||||
end else if (ex_redirect_valid) begin
|
||||
pc_q <= ex_redirect_pc;
|
||||
ifid_valid_q <= 1'b0;
|
||||
ifid_pred_taken_q <= 1'b0;
|
||||
ifid_pred_target_q <= 32'b0;
|
||||
end else if (pipeline_stall || ex_md_stall) begin
|
||||
pc_q <= pc_q;
|
||||
ifid_valid_q <= ifid_valid_q;
|
||||
ifid_pc_q <= ifid_pc_q;
|
||||
ifid_ir_q <= ifid_ir_q;
|
||||
ifid_pred_taken_q <= ifid_pred_taken_q;
|
||||
ifid_pred_target_q <= ifid_pred_target_q;
|
||||
end else if (halted_q) begin
|
||||
pc_q <= pc_q;
|
||||
ifid_valid_q <= 1'b0;
|
||||
end else begin
|
||||
pc_q <= fetch_next_pc;
|
||||
ifid_valid_q <= 1'b1;
|
||||
ifid_pc_q <= pc_q;
|
||||
ifid_ir_q <= instr_i;
|
||||
ifid_pred_taken_q <= f_is_branch && bpb_predict_hit && bpb_predict_taken;
|
||||
ifid_pred_target_q <= bpb_predict_target;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// 性能计数器（只影响统计量，不参与控制）。
|
||||
// -------------------------------------------------------------------------
|
||||
cpu21_riscv_perf_counters u_perf_counters (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.inc_cycle_i (!halted_q),
|
||||
.stall_i (pipeline_stall || ex_md_stall),
|
||||
.flush_i (flush_younger),
|
||||
.cond_taken_i (idex_valid_q && idex_branch_q && ex_branch_taken),
|
||||
.cond_valid_i (idex_valid_q && idex_branch_q),
|
||||
.mispredict_i (ex_redirect_valid),
|
||||
.uncond_i (idex_valid_q && (idex_jal_q || idex_jalr_q)),
|
||||
.cycle_count_o (cycle_count_o),
|
||||
.stall_count_o (stall_count_o),
|
||||
.bubble_count_o (bubble_count_o),
|
||||
.conditional_taken_count_o (conditional_taken_count_o),
|
||||
.unconditional_branch_count_o(unconditional_branch_count_o),
|
||||
.prediction_success_count_o (prediction_success_count_o),
|
||||
.prediction_failure_count_o (prediction_failure_count_o)
|
||||
);
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,46 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// 寄存器堆：32 x 32 位，x0 恒为 0。
|
||||
//
|
||||
// 读端口为组合读，并对同周期的 WB 写回做"写优先"旁路，因此 ID 级可以
|
||||
// 立刻看到正在写回的结果，无需额外的寄存器堆相关冒险处理。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_regfile (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
// 读端口（组合）
|
||||
input wire [ 4:0] rs1_idx_i,
|
||||
input wire [ 4:0] rs2_idx_i,
|
||||
output wire [31:0] rs1_data_o,
|
||||
output wire [31:0] rs2_data_o,
|
||||
// 写端口（WB 级）
|
||||
input wire we_i,
|
||||
input wire [ 4:0] waddr_i,
|
||||
input wire [31:0] wdata_i
|
||||
);
|
||||
reg [31:0] regs[0:31];
|
||||
|
||||
integer i;
|
||||
|
||||
// 写优先旁路：同周期写回且地址相同的读请求返回新值。
|
||||
wire [31:0] rs1_raw = regs[rs1_idx_i];
|
||||
wire [31:0] rs2_raw = regs[rs2_idx_i];
|
||||
|
||||
assign rs1_data_o = (rs1_idx_i == 5'd0) ? 32'b0 :
|
||||
((we_i && (waddr_i == rs1_idx_i)) ? wdata_i : rs1_raw);
|
||||
assign rs2_data_o = (rs2_idx_i == 5'd0) ? 32'b0 :
|
||||
((we_i && (waddr_i == rs2_idx_i)) ? wdata_i : rs2_raw);
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
for (i = 0; i < 32; i = i + 1) regs[i] <= 32'b0;
|
||||
end else begin
|
||||
if (we_i && (waddr_i != 5'd0)) regs[waddr_i] <= wdata_i;
|
||||
regs[0] <= 32'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,49 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// EX 级存储数据对齐单元。
|
||||
//
|
||||
// 依据地址低两位生成写数据与字节写掩码：sw 输出全字 + 1111，sb 把数据的
|
||||
// 低 8 位搬到对应的字节车道，并只置位对应的写掩码。
|
||||
// -----------------------------------------------------------------------------
|
||||
module cpu21_riscv_store_unit (
|
||||
input wire [31:0] addr_i,
|
||||
input wire [31:0] data_i,
|
||||
input wire mem_write_i,
|
||||
input wire mem_byte_i,
|
||||
output reg [31:0] store_data_o,
|
||||
output reg [ 3:0] store_wstrb_o
|
||||
);
|
||||
always @* begin
|
||||
store_data_o = data_i;
|
||||
store_wstrb_o = 4'b0;
|
||||
if (mem_write_i) begin
|
||||
if (mem_byte_i) begin
|
||||
case (addr_i[1:0])
|
||||
2'd0: begin
|
||||
store_data_o = {24'b0, data_i[7:0]};
|
||||
store_wstrb_o = 4'b0001;
|
||||
end
|
||||
2'd1: begin
|
||||
store_data_o = {16'b0, data_i[7:0], 8'b0};
|
||||
store_wstrb_o = 4'b0010;
|
||||
end
|
||||
2'd2: begin
|
||||
store_data_o = {8'b0, data_i[7:0], 16'b0};
|
||||
store_wstrb_o = 4'b0100;
|
||||
end
|
||||
default: begin
|
||||
store_data_o = {data_i[7:0], 24'b0};
|
||||
store_wstrb_o = 4'b1000;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
store_data_o = data_i;
|
||||
store_wstrb_o = 4'b1111;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Reference in New Issue
Block a user