`timescale 1ns / 1ps
`default_nettype none

// -----------------------------------------------------------------------------
// 性能计数器：周期数、停顿/气泡数、条件分支跳转数、无条件跳转数，
// 以及分支预测的成功/失败次数。
//
// 这些计数器只影响可观测的统计量，不参与处理器控制，便于在波形中单独
// 观察流水线效率。
// -----------------------------------------------------------------------------
module cpu21_riscv_perf_counters (
    input  wire        clk,
    input  wire        reset,
    input  wire        inc_cycle_i,                   // 未停机时周期数 +1
    input  wire        stall_i,                       // load-use 停顿
    input  wire        flush_i,                       // 冲刷年轻指令
    input  wire        cond_taken_i,                  // EX 级条件分支实际跳转
    input  wire        cond_valid_i,                  // EX 级条件分支有效
    input  wire        mispredict_i,                  // EX 级条件分支预测失败
    input  wire        uncond_i,                      // EX 级 JAL/JALR
    output wire [15:0] cycle_count_o,
    output wire [15:0] stall_count_o,
    output wire [15:0] bubble_count_o,
    output wire [15:0] conditional_taken_count_o,
    output wire [15:0] unconditional_branch_count_o,
    output wire [15:0] prediction_success_count_o,
    output wire [15:0] prediction_failure_count_o
);
  reg [15:0] cycle_count_q;
  reg [15:0] stall_count_q;
  reg [15:0] bubble_count_q;
  reg [15:0] conditional_taken_count_q;
  reg [15:0] unconditional_branch_count_q;
  reg [15:0] prediction_success_count_q;
  reg [15:0] prediction_failure_count_q;

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      cycle_count_q <= 16'b0;
      stall_count_q <= 16'b0;
      bubble_count_q <= 16'b0;
      conditional_taken_count_q <= 16'b0;
      unconditional_branch_count_q <= 16'b0;
      prediction_success_count_q <= 16'b0;
      prediction_failure_count_q <= 16'b0;
    end else begin
      if (inc_cycle_i) cycle_count_q <= cycle_count_q + 16'd1;

      if (stall_i) begin
        stall_count_q  <= stall_count_q + 16'd1;
        bubble_count_q <= bubble_count_q + 16'd1;
      end else if (flush_i) begin
        // 一次冲刷丢弃 IF/ID 两条年轻指令，记两个气泡。
        bubble_count_q <= bubble_count_q + 16'd2;
      end

      if (cond_taken_i) conditional_taken_count_q <= conditional_taken_count_q + 16'd1;
      if (uncond_i) unconditional_branch_count_q <= unconditional_branch_count_q + 16'd1;

      if (cond_valid_i) begin
        if (mispredict_i) prediction_failure_count_q <= prediction_failure_count_q + 16'd1;
        else prediction_success_count_q <= prediction_success_count_q + 16'd1;
      end
    end
  end

  assign cycle_count_o = cycle_count_q;
  assign stall_count_o = stall_count_q;
  assign bubble_count_o = bubble_count_q;
  assign conditional_taken_count_o = conditional_taken_count_q;
  assign unconditional_branch_count_o = unconditional_branch_count_q;
  assign prediction_success_count_o = prediction_success_count_q;
  assign prediction_failure_count_o = prediction_failure_count_q;
endmodule

`default_nettype wire