`timescale 1ns / 1ps
`default_nettype none

// -----------------------------------------------------------------------------
// EX 级前递单元。
//
// 优先级：EX/MEM 级的结果最新 -> 其次 MEM/WB 级写回值 -> 最后是 ID 级
// 译码时读到的寄存器值。load 结果在 MEM 级之后才可用，因此 EX/MEM 的
// load（mem_to_reg）不参与前递，改由冒险单元插入一个气泡。
// -----------------------------------------------------------------------------
module cpu21_riscv_forward_unit (
    input  wire [31:0] rs1_value_i,
    input  wire [31:0] rs2_value_i,
    input  wire [ 4:0] rs1_idx_i,
    input  wire [ 4:0] rs2_idx_i,
    // EX/MEM 级
    input  wire        exmem_valid_i,
    input  wire        exmem_reg_write_i,
    input  wire        exmem_mem_to_reg_i,
    input  wire [ 4:0] exmem_rd_i,
    input  wire [31:0] exmem_value_i,
    // MEM/WB 级
    input  wire        memwb_valid_i,
    input  wire        memwb_reg_write_i,
    input  wire [ 4:0] memwb_rd_i,
    input  wire [31:0] memwb_value_i,
    // 前递后的操作数
    output reg  [31:0] src1_o,
    output reg  [31:0] src2_o
);
  wire ex_mem_forward_valid = exmem_valid_i && exmem_reg_write_i &&
                                !exmem_mem_to_reg_i && (exmem_rd_i != 5'd0);
  wire wb_forward_valid = memwb_valid_i && memwb_reg_write_i && (memwb_rd_i != 5'd0);

  always @* begin
    src1_o = rs1_value_i;
    src2_o = rs2_value_i;

    if (ex_mem_forward_valid && (exmem_rd_i == rs1_idx_i)) src1_o = exmem_value_i;
    else if (wb_forward_valid && (memwb_rd_i == rs1_idx_i)) src1_o = memwb_value_i;

    if (ex_mem_forward_valid && (exmem_rd_i == rs2_idx_i)) src2_o = exmem_value_i;
    else if (wb_forward_valid && (memwb_rd_i == rs2_idx_i)) src2_o = memwb_value_i;
  end
endmodule

`default_nettype wire