diff --git a/pipelined-cpu/create_project.tcl b/pipelined-cpu/create_project.tcl index 5580901..23c0e8b 100644 --- a/pipelined-cpu/create_project.tcl +++ b/pipelined-cpu/create_project.tcl @@ -1,6 +1,6 @@ # ============================================================================ # cpu21-riscv 流水线 CPU —— 一键重建 Vivado 工程 -# FPGA:Nexys4DDR / xc7a100tcsg324-1(Vivado 2025.2 实测通过) +# FPGA:Nexys4DDR / xc7a100tcsg324-1(Vivado 2020.2 实测:建工程 + 综合均通过) # # 目录结构(本脚本所在目录就是工程目录): # create_project.tcl 本脚本 diff --git a/pipelined-cpu/srcs/rtl/cpu21_ps2_mouse.v b/pipelined-cpu/srcs/rtl/cpu21_ps2_mouse.v index 4e8e788..80aa06c 100644 --- a/pipelined-cpu/srcs/rtl/cpu21_ps2_mouse.v +++ b/pipelined-cpu/srcs/rtl/cpu21_ps2_mouse.v @@ -110,7 +110,9 @@ module cpu21_ps2_mouse ( case (byte_cnt_q) 8'd0: begin // 标志字节:bit3 必须为 1(否则是鼠标发来的其他响应,丢弃) - if (frame_q[8:1][3] == 1'b1) begin + // 数据字节 = frame_q[8:1],它的 bit3 就是 frame_q[4] + // (不能写 frame_q[8:1][3]:Verilog-2001 不允许 part-select 再取位) + if (frame_q[4] == 1'b1) begin pkt_q[7:0] <= frame_q[8:1]; byte_cnt_q <= 8'd1; end @@ -121,9 +123,10 @@ module cpu21_ps2_mouse ( end 8'd2: begin byte_cnt_q <= 8'd0; - ev_dx_o <= frame_q[8:1]; // dy - ev_dy_o <= pkt_q[15:8]; // 注意:byte1 是 dx - ev_btn_o <= {2'b0, pkt_q[2], pkt_q[1]}; // {middle, right, left} + ev_dx_o <= pkt_q[15:8]; // byte1 = dx + ev_dy_o <= frame_q[8:1]; // byte2 = dy + // 与 cpu21_mmio / mmio.h 一致:bit0=左键, bit1=右键, bit2=中键 + ev_btn_o <= {2'b0, pkt_q[2], pkt_q[1], pkt_q[0]}; ev_valid_o <= 1'b1; end default: diff --git a/pipelined-cpu/tools/check_rtl_text.ps1 b/pipelined-cpu/tools/check_rtl_text.ps1 index 99745cd..4eeff15 100644 --- a/pipelined-cpu/tools/check_rtl_text.ps1 +++ b/pipelined-cpu/tools/check_rtl_text.ps1 @@ -53,6 +53,8 @@ foreach ($f in $files) { else { $c = $code.IndexOf('//'); if ($c -ge 0) { $code = $code.Substring(0, $c) } } + # 字符串字面量里的中文是合法的(如 $display("中文")),先去掉再判断 + $code = $code -replace '"[^"]*"', '""' $trim = $line.Trim()