From 0908580e4648b02be94b3cf0c87cea79c2369de3 Mon Sep 17 00:00:00 2001 From: Alex-create-beep <2965312221@qq.com> Date: Sat, 19 Sep 2026 19:50:37 +0800 Subject: [PATCH] =?UTF-8?q?tcl:=20=E6=96=B0=E5=A2=9E=E6=89=AB=E9=9B=B7?= =?UTF-8?q?=E4=B8=93=E7=94=A8=E5=BB=BA=E5=B7=A5=E7=A8=8B=E8=84=9A=E6=9C=AC?= =?UTF-8?q?=20+=20=E4=BF=AE=E6=96=87=E6=9C=AC=E8=87=AA=E6=A3=80=E8=AF=AF?= =?UTF-8?q?=E6=8A=A5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - create_project_saolei.tcl:独立工程 pipelined-cpu-saolei,只装配扫雷所需源文件, sources_1/sim_1 都固定定义 SAOLEI_ROM,sim_1 顶层 = tb_saolei;先清理旧工程再新建 (实测:建工程 + 综合均通过,0 error / 0 critical warning) - check_rtl_text.ps1:不再把 Verilog 延时语法 #10 / #(expr) / #delay 误报成粘贴正文 - create_project.tcl:默认程序切回中断测试 ccab --- pipelined-cpu/create_project.tcl | 4 ++-- pipelined-cpu/tools/check_rtl_text.ps1 | 9 ++++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/pipelined-cpu/create_project.tcl b/pipelined-cpu/create_project.tcl index e437a09..b885a4f 100644 --- a/pipelined-cpu/create_project.tcl +++ b/pipelined-cpu/create_project.tcl @@ -134,8 +134,8 @@ set_property file_type {Verilog Header} \ # use_intrupt_ccab = 1 -> 上一版中断测试(programs/risc-v-intrupt-ccab.*) # use_saolei = 1 -> 扫雷(saolei/tools/build.ps1 生成) # 三个都为 0 -> 走马灯 demo -set use_intrupt_sllsb 1 -set use_intrupt_ccab 0 +set use_intrupt_sllsb 0 +set use_intrupt_ccab 1 set use_saolei 0 # 中断测试程序的 ROM 初始化。 diff --git a/pipelined-cpu/tools/check_rtl_text.ps1 b/pipelined-cpu/tools/check_rtl_text.ps1 index 4eeff15..c5a8e00 100644 --- a/pipelined-cpu/tools/check_rtl_text.ps1 +++ b/pipelined-cpu/tools/check_rtl_text.ps1 @@ -11,8 +11,9 @@ # WHAT IT CHECKS # 1) a line inside .v/.vh/.xdc that has non-ASCII characters *outside* a comment # (i.e. real code position) -> corruption; -# 2) a line that looks like pasted prose/markdown (leading "|", "**", or a line -# that is bare text after `endmodule`). +# 2) a line that looks like pasted prose/markdown (leading "|", "**", or a bare +# "#" that is NOT a Verilog delay/parameter override: #10, #(expr), #delay are +# legal Verilog, so only "#" followed by something else (space, CJK...) is flagged). # # USAGE (from the repository root or from pipelined-cpu/): # powershell -ExecutionPolicy Bypass -File pipelined-cpu\tools\check_rtl_text.ps1 @@ -71,7 +72,9 @@ foreach ($f in $files) { } # ---- check 2: pasted prose / markdown leftovers ---- - if ($trim -match '^\||^\*\*|^#[^0-9#]' -and $f.Extension -ne '.xdc') { + # 注意:.v/.vh 里 "#" 是合法的延时语法(#10 / #(expr) / #delay), + # 只有 "#" 后面跟着空格/中文等非代码字符才当成注释残留。 + if ($trim -match '^\||^\*\*|^#[^0-9(A-Za-z_]' -and $f.Extension -ne '.xdc') { Write-Output ("!! $rel`:$lineNo looks like pasted prose:") Write-Output (" " + $trim) $bad++