diff --git a/pipelined-cpu/create_project.tcl b/pipelined-cpu/create_project.tcl
index e437a09..b885a4f 100644
--- a/pipelined-cpu/create_project.tcl
+++ b/pipelined-cpu/create_project.tcl
@@ -134,8 +134,8 @@ set_property file_type {Verilog Header} \
 #   use_intrupt_ccab  = 1 -> 上一版中断测试（programs/risc-v-intrupt-ccab.*）
 #   use_saolei        = 1 -> 扫雷（saolei/tools/build.ps1 生成）
 #   三个都为 0            -> 走马灯 demo
-set use_intrupt_sllsb 1
-set use_intrupt_ccab 0
+set use_intrupt_sllsb 0
+set use_intrupt_ccab 1
 set use_saolei 0
 
 # 中断测试程序的 ROM 初始化。
diff --git a/pipelined-cpu/tools/check_rtl_text.ps1 b/pipelined-cpu/tools/check_rtl_text.ps1
index 4eeff15..c5a8e00 100644
--- a/pipelined-cpu/tools/check_rtl_text.ps1
+++ b/pipelined-cpu/tools/check_rtl_text.ps1
@@ -11,8 +11,9 @@
 # WHAT IT CHECKS
 #   1) a line inside .v/.vh/.xdc that has non-ASCII characters *outside* a comment
 #      (i.e. real code position) -> corruption;
-#   2) a line that looks like pasted prose/markdown (leading "|", "**", or a line
-#      that is bare text after `endmodule`).
+#   2) a line that looks like pasted prose/markdown (leading "|", "**", or a bare
+#      "#" that is NOT a Verilog delay/parameter override: #10, #(expr), #delay are
+#      legal Verilog, so only "#" followed by something else (space, CJK...) is flagged).
 #
 # USAGE (from the repository root or from pipelined-cpu/):
 #   powershell -ExecutionPolicy Bypass -File pipelined-cpu\tools\check_rtl_text.ps1
@@ -71,7 +72,9 @@ foreach ($f in $files) {
         }
 
         # ---- check 2: pasted prose / markdown leftovers ----
-        if ($trim -match '^\||^\*\*|^#[^0-9#]' -and $f.Extension -ne '.xdc') {
+        # 注意：.v/.vh 里 "#" 是合法的延时语法（#10 / #(expr) / #delay），
+        # 只有 "#" 后面跟着空格/中文等非代码字符才当成注释残留。
+        if ($trim -match '^\||^\*\*|^#[^0-9(A-Za-z_]' -and $f.Extension -ne '.xdc') {
             Write-Output ("!! $rel`:$lineNo  looks like pasted prose:")
             Write-Output ("        " + $trim)
             $bad++